From patchwork Thu Sep 22 21:04:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= X-Patchwork-Id: 9346961 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1F8F9601C2 for ; Thu, 22 Sep 2016 21:09:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BADA2ACB8 for ; Thu, 22 Sep 2016 21:09:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00BC52ACD2; Thu, 22 Sep 2016 21:09:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 72CED2ACB8 for ; Thu, 22 Sep 2016 21:09:40 +0000 (UTC) Received: from localhost ([::1]:33861 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnBFT-0000M1-Ln for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Sep 2016 17:09:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51205) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnBCQ-0006JE-RU for qemu-devel@nongnu.org; Thu, 22 Sep 2016 17:06:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bnBCJ-00088U-2G for qemu-devel@nongnu.org; Thu, 22 Sep 2016 17:06:28 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59030) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnBBL-0007W0-Gq for qemu-devel@nongnu.org; Thu, 22 Sep 2016 17:06:22 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AAFC23D1CE; Thu, 22 Sep 2016 21:05:02 +0000 (UTC) Received: from potion (ovpn-204-106.brq.redhat.com [10.40.204.106]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with SMTP id u8ML4xfD025264; Thu, 22 Sep 2016 17:05:00 -0400 Received: by potion (sSMTP sendmail emulation); Thu, 22 Sep 2016 23:04:59 +0200 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: qemu-devel@nongnu.org Date: Thu, 22 Sep 2016 23:04:31 +0200 Message-Id: <20160922210432.18680-5-rkrcmar@redhat.com> In-Reply-To: <20160922210432.18680-1-rkrcmar@redhat.com> References: <20160922210432.18680-1-rkrcmar@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Thu, 22 Sep 2016 21:05:02 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 4/5] intel_iommu: add "eim" property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "Michael S. Tsirkin" , Peter Xu , Paolo Bonzini , Igor Mammedov , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Peter Xu Adding one extra property for intel-iommu device to decide whether we should support EIM bit for IR. Now we are throwing high 24 bits of dest_id away directly. This will cause interrupt issues with guests that: - enabled x2apic with cluster mode - have more than 8 vcpus (so dest_id[31:8] might be nonzero) Let's make xapic the default one, and for the brave people who would like to try EIM and know the side effects, we can do it by explicitly enabling EIM using: -device intel-iommu,intremap=on,eim=on Even after we have x2apic support, it'll still be good if we can provide a way to switch xapic/x2apic from QEMU side for e.g. debugging purpose, which is an alternative for tuning guest kernel boot parameters. We can switch the default to "on" after x2apic fully supported. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 16 +++++++++++++++- include/hw/i386/intel_iommu.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1a0961e5cf6a..269e37e71af4 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2004,6 +2004,11 @@ static const MemoryRegionOps vtd_mem_ops = { static Property vtd_properties[] = { DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0), + /* + * TODO: currently EIM is disabled by default. We can enable this + * after fully support x2apic. + */ + DEFINE_PROP_BOOL("eim", IntelIOMMUState, eim_supported, false), DEFINE_PROP_END_OF_LIST(), }; @@ -2360,7 +2365,10 @@ static void vtd_init(IntelIOMMUState *s) s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; if (x86_iommu->intr_supported) { - s->ecap |= VTD_ECAP_IR | VTD_ECAP_EIM | VTD_ECAP_MHMV; + s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; + if (s->eim_supported) { + s->ecap |= VTD_ECAP_EIM; + } } vtd_reset_context_cache(s); @@ -2464,6 +2472,12 @@ static void vtd_realize(DeviceState *dev, Error **errp) /* Pseudo address space under root PCI bus. */ pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC); + /* EIM bit requires IR */ + if (s->eim_supported && !x86_iommu->intr_supported) { + error_report("EIM (Extended Interrupt Mode) bit requires intremap=on"); + exit(1); + } + /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */ if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() && !kvm_irqchip_is_split()) { diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index a42dbd745a70..b1bc76895deb 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -289,6 +289,7 @@ struct IntelIOMMUState { dma_addr_t intr_root; /* Interrupt remapping table pointer */ uint32_t intr_size; /* Number of IR table entries */ bool intr_eime; /* Extended interrupt mode enabled */ + bool eim_supported; /* Whether to allow EIM bit */ }; /* Find the VTD Address space associated with the given bus pointer,