From patchwork Mon Sep 26 07:17:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rabin Vincent X-Patchwork-Id: 9350175 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AE8F56077B for ; Mon, 26 Sep 2016 07:19:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 98B0A28BC7 for ; Mon, 26 Sep 2016 07:19:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8CE8428C4A; Mon, 26 Sep 2016 07:19:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D8AA228BC7 for ; Mon, 26 Sep 2016 07:19:34 +0000 (UTC) Received: from localhost ([::1]:41909 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1boQCL-0001Bt-Vf for patchwork-qemu-devel@patchwork.kernel.org; Mon, 26 Sep 2016 03:19:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59092) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1boQAW-00008v-Mh for qemu-devel@nongnu.org; Mon, 26 Sep 2016 03:17:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1boQAS-0003bW-FK for qemu-devel@nongnu.org; Mon, 26 Sep 2016 03:17:39 -0400 Received: from bastet.se.axis.com ([195.60.68.11]:41479) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1boQAS-0003aP-4j for qemu-devel@nongnu.org; Mon, 26 Sep 2016 03:17:36 -0400 Received: from localhost (localhost [127.0.0.1]) by bastet.se.axis.com (Postfix) with ESMTP id DF050180A2; Mon, 26 Sep 2016 09:17:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bastet.se.axis.com Received: from bastet.se.axis.com ([IPv6:::ffff:127.0.0.1]) by localhost (bastet.se.axis.com [::ffff:127.0.0.1]) (amavisd-new, port 10024) with LMTP id o3VKZ1rY8jeF; Mon, 26 Sep 2016 09:17:33 +0200 (CEST) Received: from boulder03.se.axis.com (boulder03.se.axis.com [10.0.8.17]) by bastet.se.axis.com (Postfix) with ESMTPS id D12951809C; Mon, 26 Sep 2016 09:17:33 +0200 (CEST) Received: from boulder03.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BBD9A1E090; Mon, 26 Sep 2016 09:17:33 +0200 (CEST) Received: from boulder03.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B09C01E08F; Mon, 26 Sep 2016 09:17:33 +0200 (CEST) Received: from thoth.se.axis.com (unknown [10.0.2.173]) by boulder03.se.axis.com (Postfix) with ESMTP; Mon, 26 Sep 2016 09:17:33 +0200 (CEST) Received: from lnxartpec.se.axis.com (lnxartpec.se.axis.com [10.88.4.9]) by thoth.se.axis.com (Postfix) with ESMTP id A4C842F9; Mon, 26 Sep 2016 09:17:33 +0200 (CEST) Received: by lnxartpec.se.axis.com (Postfix, from userid 10564) id 9CE988049C; Mon, 26 Sep 2016 09:17:33 +0200 (CEST) Date: Mon, 26 Sep 2016 09:17:33 +0200 From: Rabin Vincent To: "Edgar E. Iglesias" Message-ID: <20160926071733.GB4538@axis.com> References: <1473076452-19795-1-git-send-email-rabin.vincent@axis.com> <1473076452-19795-8-git-send-email-rabin.vincent@axis.com> <20160912221800.GK16305@toto> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20160912221800.GK16305@toto> User-Agent: Mutt/1.5.23 (2014-03-12) X-TM-AS-GCONF: 00 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.60.68.11 Subject: Re: [Qemu-devel] [PATCH 8/9] target-cris: add v17 CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP On Tue, Sep 13, 2016 at 12:18:00AM +0200, Edgar E. Iglesias wrote: > On Mon, Sep 05, 2016 at 01:54:11PM +0200, Rabin Vincent wrote: > > diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c > > index a3da425..33d86eb 100644 > > --- a/target-cris/translate_v10.c > > +++ b/target-cris/translate_v10.c > > @@ -1097,6 +1097,14 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) > > insn_len = dec10_bdap_m(env, dc, size); > > break; > > default: > > + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 && > > + env->pregs[PR_VR] == 17) { > > Could you please add some comments on the insn encoding? > Put the stuff from the commit msg in here. OK, see new patch below. > IIRC, ADDC and v17 are modifications made to the CRISv10 family of > cores that never made it into the public manuals. Or am I wrong? No, you're right. 8<--------------- From 513465ad3f007885bafba3482705ba57cacd588b Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Mon, 15 Aug 2016 13:59:32 +0200 Subject: [PATCH] target-cris: add v17 CPU In the CRIS v17 CPU an ADDC (add with carry) instruction has been added compared to the v10 instruction set. Assembler syntax: ADDC [Rs],Rd ADDC [Rs+],Rd Size: Dword Description: The source data is added together with the carry flag to the destination register. The size of the operation is dword. Operation: Rd += s + C-flag; Flags affected: S R P U I X N Z V C - - - - - 0 * * * * Instruction format: ADDC [Rs],Rd +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Instruction format: ADDC [Rs+],Rd +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Signed-off-by: Rabin Vincent --- target-cris/cpu.c | 14 ++++++++++++++ target-cris/crisv10-decode.h | 1 + target-cris/translate_v10.c | 23 +++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index c5a656b..d680cfb 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = crisv10_cpu_gdb_read_register; } +static void crisv17_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); + + ccc->vr = 17; + cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; +} + static void crisv32_cpu_class_init(ObjectClass *oc, void *data) { CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); @@ -273,6 +283,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = { .parent = TYPE_CRIS_CPU, .class_init = crisv11_cpu_class_init, }, { + .name = TYPE("crisv17"), + .parent = TYPE_CRIS_CPU, + .class_init = crisv17_cpu_class_init, + }, { .name = TYPE("crisv32"), .parent = TYPE_CRIS_CPU, .class_init = crisv32_cpu_class_init, diff --git a/target-cris/crisv10-decode.h b/target-cris/crisv10-decode.h index 587fbdd..bdb4b6d 100644 --- a/target-cris/crisv10-decode.h +++ b/target-cris/crisv10-decode.h @@ -92,6 +92,7 @@ #define CRISV10_IND_JUMP_M 4 #define CRISV10_IND_DIP 5 #define CRISV10_IND_JUMP_R 6 +#define CRISV17_IND_ADDC 6 #define CRISV10_IND_BOUND 7 #define CRISV10_IND_BCC_M 7 #define CRISV10_IND_MOVE_M_SPR 8 diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index 4707a18..0e4d039 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -1094,6 +1094,29 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) insn_len = dec10_bdap_m(env, dc, size); break; default: + /* + * ADDC for v17: + * + * Instruction format: ADDC [Rs],Rd + * + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) | + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * + * Instruction format: ADDC [Rs+],Rd + * + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) | + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ + */ + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 && + env->pregs[PR_VR] == 17) { + LOG_DIS("addc op=%d %d\n", dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size); + break; + } + LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", dc->pc, size, dc->opcode, dc->src, dc->dst); cpu_abort(CPU(dc->cpu), "Unhandled opcode");