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Wed, 19 Oct 2016 23:59:32 -0700 (PDT) Received: from roar.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id u10sm68754223pau.32.2016.10.19.23.59.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 23:59:32 -0700 (PDT) From: Nicholas Piggin To: qemu-devel@nongnu.org Date: Thu, 20 Oct 2016 17:59:10 +1100 Message-Id: <20161020065912.16132-2-npiggin@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161020065912.16132-1-npiggin@gmail.com> References: <20161020065912.16132-1-npiggin@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::242 X-Mailman-Approved-At: Thu, 20 Oct 2016 10:46:21 -0400 Subject: [Qemu-devel] [PATCH 1/3] ppc: fix MSR_ME handling for system reset interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , qemu-ppc@nongnu.org, Alexander Graf , Nicholas Piggin , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Power ISA specifies ME bit handling for system reset interrupt: if the interrupt occurred while the thread was in power-saving mode, set to 1; otherwise not altered Signed-off-by: Nicholas Piggin --- target-ppc/excp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 921c39d..53c4075 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -385,11 +385,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) srr1 = SPR_BOOKE_CSRR1; break; case POWERPC_EXCP_RESET: /* System reset exception */ + /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { /* indicate that we resumed from power save mode */ msr |= 0x10000; - } else { - new_msr &= ~((target_ulong)1 << MSR_ME); + new_msr |= ((target_ulong)1 << MSR_ME); } new_msr |= (target_ulong)MSR_HVB;