From patchwork Thu Oct 27 12:50:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 9399261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2F2FE60588 for ; Thu, 27 Oct 2016 12:54:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 12A2A2A26D for ; Thu, 27 Oct 2016 12:54:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 03C1F2A26F; Thu, 27 Oct 2016 12:54:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9BA102A26D for ; Thu, 27 Oct 2016 12:54:01 +0000 (UTC) Received: from localhost ([::1]:41256 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzkC0-0000Uh-JZ for patchwork-qemu-devel@patchwork.kernel.org; Thu, 27 Oct 2016 08:54:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzk9T-0007PF-3b for qemu-devel@nongnu.org; Thu, 27 Oct 2016 08:51:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzk9P-0003D0-VH for qemu-devel@nongnu.org; Thu, 27 Oct 2016 08:51:23 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:32936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bzk9P-0003CX-P5; Thu, 27 Oct 2016 08:51:19 -0400 Received: by mail-pf0-x242.google.com with SMTP id i85so2623076pfa.0; Thu, 27 Oct 2016 05:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=BIUTEtkZsxry8JuF8Ax5yf3c4bvL7e5+gHmx6MUh/Gc=; b=sMrZRvN1mjmhoF8yYaaXt++uiEUufGOF4qSRl/SLtylJvWvDtsikPtBGfeKyn1t6tz FDqZKkHhOgnTuyRXwT6ig1TUq7/CB/jxnNppfPTLCnpfhdQaX0uHu7zMCAYgMrh3TH8/ sylBNOGvELWcVlqcp+g7GZcc5wPNA3NlnSZ+/DaYjPt4LhrC3VkNtrkY99ye/tW56ynT XOLnuUeIi6MyzUx/q7VKQSN1bD+GXPMHIJsBTLZZPT79FUwpV3XBkx0Re5aIYtHB2SbV /pElQHxVgP/0g6zV/mpVqwP+iwqyLfLAXtgv2j9hAemAuDw8i/KnpCPfsA7f6mS7vGvO ZnbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=BIUTEtkZsxry8JuF8Ax5yf3c4bvL7e5+gHmx6MUh/Gc=; b=KA2e2zDa/AW2Q7LZ6mmSQH5nkOv0Dan6AvcDkV1zXsIEARTsmzNG6WQHtd3bM049IK h7H0yD8mfjo3mQ0ZpVdYmBSvgpsOd95Nzt27tWkNS88yiNlGZkxS62PdIEjLOiJuFxU8 ocYfIYpDkryAyIT6LQXvXr2f7Wu+9MbbmotjdLLMe3C1RXa5qYSJj9EdzWJTgYfDAXec Cnz8XCbioL8tuVBSCgs9O70t9VOzoce2Mr56m+HTqoL7Q43iiT7XCqtDhJlWDrWkqGqR 4ZxqYd2wbGKdL57f5rB+MfuazU6p4U9HSfSn2/QdFLFaHoialrg00Xlua22auVGtDErd fiBg== X-Gm-Message-State: ABUngveLp6Z/kJezxV8phfRontyP8iIm9BzKA/TirZzig0bu88Lr/t9xZepGSk0ivnsHKA== X-Received: by 10.99.242.5 with SMTP id v5mr11772081pgh.137.1477572678317; Thu, 27 Oct 2016 05:51:18 -0700 (PDT) Received: from roar.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id g78sm11771174pfe.19.2016.10.27.05.51.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Oct 2016 05:51:17 -0700 (PDT) From: Nicholas Piggin To: David Gibson Date: Thu, 27 Oct 2016 23:50:58 +1100 Message-Id: <20161027125058.11274-1-npiggin@gmail.com> X-Mailer: git-send-email 2.9.3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3] ppc: allow certain HV interrupts to be delivered to guests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , qemu-devel@nongnu.org, Nicholas Piggin , qemu-ppc@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP ppc hypervisors have delivered system reset and machine check exception interrupts to guests in some situations (e.g., see FWNMI feature of LoPAPR, or NMI injection in QEMU). These exceptions are architected to set the HV bit in hardware, however when injected into a guest, the HV bit should be cleared. Current code masks off the HV bit before setting the new MSR, however this happens after the interrupt delivery model has calculated delivery mode for the exception. This can result in the guest's MSR LE bit being lost. Account for this in the exception handler and don't set HV bit for guest delivery. Also add another sanity check to ensure similar bugs get caught. Signed-off-by: Nicholas Piggin --- v3: David and I discussed this more on IRC, and agreed it's better to keep such important MSR bit settings in the exception handler cases themselves. Having to follow the "guest_hv_excp" logic is extra distraction and doesn't buy any significant code reuse. target-ppc/excp_helper.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 53c4075..808760b 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -213,7 +213,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) cs->halted = 1; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } - new_msr |= (target_ulong)MSR_HVB; + if (env->msr_mask & MSR_HVB) { + /* ISA specifies HV, but can be delivered to guest with HV clear + * (e.g., see FWNMI in PAPR). + */ + new_msr |= (target_ulong)MSR_HVB; + } ail = 0; /* machine check exceptions don't have ME set */ @@ -391,8 +396,17 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) msr |= 0x10000; new_msr |= ((target_ulong)1 << MSR_ME); } - - new_msr |= (target_ulong)MSR_HVB; + if (env->msr_mask & MSR_HVB) { + /* ISA specifies HV, but can be delivered to guest with HV clear + * (e.g., see FWNMI in PAPR, NMI injection in QEMU). + */ + new_msr |= (target_ulong)MSR_HVB; + } else { + if (msr_pow) { + cpu_abort(cs, "Trying to deliver power-saving system reset " + "exception %d with no HV support\n", excp); + } + } ail = 0; break; case POWERPC_EXCP_DSEG: /* Data segment exception */ @@ -609,9 +623,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) env->spr[srr1] = msr; /* Sanity check */ - if (!(env->msr_mask & MSR_HVB) && (srr0 == SPR_HSRR0)) { - cpu_abort(cs, "Trying to deliver HV exception %d with " - "no HV support\n", excp); + if (!(env->msr_mask & MSR_HVB)) { + if (new_msr & MSR_HVB) { + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " + "no HV support\n", excp); + } + if (srr0 == SPR_HSRR0) { + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " + "no HV support\n", excp); + } } /* If any alternate SRR register are defined, duplicate saved values */