From patchwork Wed Feb 22 06:33:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 9586319 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB08A6020B for ; Wed, 22 Feb 2017 07:13:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C99C52875D for ; Wed, 22 Feb 2017 07:13:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BE16B2883A; Wed, 22 Feb 2017 07:13:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 27A692875D for ; Wed, 22 Feb 2017 07:13:25 +0000 (UTC) Received: from localhost ([::1]:50338 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgR76-0000vP-40 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 22 Feb 2017 02:13:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38043) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cgQVB-00038k-Om for qemu-devel@nongnu.org; Wed, 22 Feb 2017 01:34:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cgQV9-0008Bt-Ie for qemu-devel@nongnu.org; Wed, 22 Feb 2017 01:34:13 -0500 Received: from ozlabs.org ([103.22.144.67]:33813) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cgQV8-00084f-4d; Wed, 22 Feb 2017 01:34:11 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3vSndL5bYjz9sNB; Wed, 22 Feb 2017 17:33:56 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1487745238; bh=88hqjLjXFHdCI2YgvI3o+13sTRqA2sYhmUTqlCDPNrI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NFTvJsVTUeqZwy1jEjN0jLTaoRPVWLP0PaS8Qv6xPSbdx4/tEOANHutnHW7YVfged TOoiQrP7DmTxnoZK+xak20l7RQ2J4F9eiDgjP4Aq3lDxorHZ2ErpEuPjzUuIP+uW9L TgQkyDoaeVWDdGJlnaRJ6FsAOIk343qQswnAMrXw= From: David Gibson To: peter.maydell@linaro.org Date: Wed, 22 Feb 2017 17:33:33 +1100 Message-Id: <20170222063348.32176-29-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170222063348.32176-1-david@gibson.dropbear.id.au> References: <20170222063348.32176-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 28/43] target/ppc/POWER9: Add ISAv3.00 MMU definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, mdroth@linux.vnet.ibm.com, agraf@suse.de, qemu-ppc@nongnu.org, Suraj Jitindar Singh , imammedo@redhat.com, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Suraj Jitindar Singh POWER9 processors implement the mmu as defined in version 3.00 of the ISA. Add a definition for this mmu model and set the POWER9 cpu model to use this mmu model. Signed-off-by: Suraj Jitindar Singh Signed-off-by: David Gibson --- target/ppc/cpu-qom.h | 5 ++++- target/ppc/mmu_helper.c | 2 ++ target/ppc/translate_init.c | 3 +-- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index b7977ba..4e3132b 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -86,10 +86,13 @@ enum powerpc_mmu_t { POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, - /* FIXME Add POWERPC_MMU_3_OO defines */ /* Architecture 2.07 "degraded" (no 1T segments) */ POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x00000004, + /* Architecture 3.00 variant */ + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG + | POWERPC_MMU_64K + | POWERPC_MMU_AMR | 0x00000005, }; /*****************************************************************************/ diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f746f53..172a305 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1935,6 +1935,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: #endif /* defined(TARGET_PPC64) */ env->tlb_need_flush = 0; tlb_flush(CPU(cpu)); @@ -1974,6 +1975,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 76f79fa..84bf125 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8816,8 +8816,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - /* Using 2.07 defines until new radix model is added. */ - pcc->mmu_model = POWERPC_MMU_2_07; + pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; /* segment page size remain the same */