| Message ID | 20170302195337.31558-3-alex.bennee@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Mar 02, 2017 at 07:53:28PM +0000, Alex Bennée wrote: > This suppresses the incorrect warning when forcing MTTCG for x86 > guests on x86 hosts. A future patch will still warn when > TARGET_SUPPORT_MTTCG hasn't been defined for the guest (which is still > pending for x86). > > Reported-by: Paolo Bonzini <pbonzini@redhat.com> > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> I assume the whole series is going to be merged through the same tree, so: Acked-by: Eduardo Habkost <ehabkost@redhat.com> > --- > target/i386/cpu.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 12a39d590f..ecdd3bbc2a 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -30,6 +30,9 @@ > #define TARGET_LONG_BITS 32 > #endif > > +/* The x86 has a strong memory model with some store-after-load re-ordering */ > +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) > + > /* Maximum instruction code size */ > #define TARGET_MAX_INSN_SIZE 16 > > -- > 2.11.0 >
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 12a39d590f..ecdd3bbc2a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -30,6 +30,9 @@ #define TARGET_LONG_BITS 32 #endif +/* The x86 has a strong memory model with some store-after-load re-ordering */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + /* Maximum instruction code size */ #define TARGET_MAX_INSN_SIZE 16