From patchwork Mon Mar 13 19:55:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Blake X-Patchwork-Id: 9622025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0448660244 for ; Mon, 13 Mar 2017 20:06:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE3F426E56 for ; Mon, 13 Mar 2017 20:06:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E2C3528236; Mon, 13 Mar 2017 20:06:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 84CE726E56 for ; Mon, 13 Mar 2017 20:06:17 +0000 (UTC) Received: from localhost ([::1]:54152 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnWES-0000aZ-Ie for patchwork-qemu-devel@patchwork.kernel.org; Mon, 13 Mar 2017 16:06:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cnW4e-0000iO-BH for qemu-devel@nongnu.org; Mon, 13 Mar 2017 15:56:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cnW4d-0002WT-9g for qemu-devel@nongnu.org; Mon, 13 Mar 2017 15:56:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47210) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cnW4d-0002VX-28 for qemu-devel@nongnu.org; Mon, 13 Mar 2017 15:56:07 -0400 Received: from smtp.corp.redhat.com (int-mx16.intmail.prod.int.phx2.redhat.com [10.5.11.28]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F2ECE65383 for ; Mon, 13 Mar 2017 19:56:06 +0000 (UTC) Received: from red.redhat.com (unknown [10.10.121.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 49C042D5C6; Mon, 13 Mar 2017 19:56:06 +0000 (UTC) From: Eric Blake To: qemu-devel@nongnu.org Date: Mon, 13 Mar 2017 14:55:30 -0500 Message-Id: <20170313195547.21466-14-eblake@redhat.com> In-Reply-To: <20170313195547.21466-1-eblake@redhat.com> References: <20170313195547.21466-1-eblake@redhat.com> X-Scanned-By: MIMEDefang 2.74 on 10.5.11.28 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Mon, 13 Mar 2017 19:56:07 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 13/30] trace: Fix parameter types in hw/char X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , stefanha@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP An upcoming patch will let the compiler warn us when we are silently losing precision in traces. In most cases, we just update the trace definitions to match the caller types; but in one case, the caller had already done 'val &= 0xff' so casting uint64_t val down to the type expected by the trace is sufficient. Signed-off-by: Eric Blake --- hw/char/escc.c | 4 ++-- hw/char/trace-events | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/char/escc.c b/hw/char/escc.c index 9228091..33a4d20 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -483,7 +483,7 @@ static void escc_mem_write(void *opaque, hwaddr addr, s = &serial->chn[channel]; switch (saddr) { case SERIAL_CTRL: - trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff); + trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, (uint8_t) val); newreg = 0; switch (s->reg) { case W_CMD: @@ -553,7 +553,7 @@ static void escc_mem_write(void *opaque, hwaddr addr, s->reg = 0; break; case SERIAL_DATA: - trace_escc_mem_writeb_data(CHN_C(s), val); + trace_escc_mem_writeb_data(CHN_C(s), (uint8_t) val); s->tx = val; if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled if (qemu_chr_fe_get_driver(&s->chr)) { diff --git a/hw/char/trace-events b/hw/char/trace-events index 7fd48bb..361eee0 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -13,7 +13,7 @@ virtio_console_chr_event(unsigned int port, int event) "port %u, event %d" # hw/char/grlib_apbuart.c grlib_apbuart_event(int event) "event:%d" -grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x" +grlib_apbuart_writel_unknown(uint64_t addr, uint64_t value) "addr 0x%"PRIx64" value 0x%" PRIx64 grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 # hw/char/lm32_juart.c @@ -23,13 +23,13 @@ lm32_juart_get_jrx(uint32_t value) "jrx 0x%08x" lm32_juart_set_jrx(uint32_t value) "jrx 0x%08x" # hw/char/lm32_uart.c -lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" -lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +lm32_uart_memory_write(hwaddr addr, uint64_t value) "addr 0x%08" HWADDR_PRIx " value 0x%08" PRIx64 +lm32_uart_memory_read(hwaddr addr, uint32_t value) "addr 0x%08" HWADDR_PRIx " value 0x%08x" lm32_uart_irq_state(int level) "irq state %d" # hw/char/milkymist-uart.c -milkymist_uart_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x" -milkymist_uart_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x" +milkymist_uart_memory_read(hwaddr addr, uint32_t value) "addr %08" HWADDR_PRIx " value %08x" +milkymist_uart_memory_write(hwaddr addr, uint64_t value) "addr %08" HWADDR_PRIx " value %08" PRIx64 milkymist_uart_raise_irq(void) "Raise IRQ" milkymist_uart_lower_irq(void) "Lower IRQ" @@ -50,9 +50,9 @@ escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=%01x # hw/char/pl011.c pl011_irq_state(int level) "irq state %d" -pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_read(hwaddr addr, uint64_t value) "addr 0x%08" HWADDR_PRIx " value 0x%08" PRIx64 pl011_read_fifo(int read_count) "FIFO read, read_count now %d" -pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_write(hwaddr addr, uint64_t value) "addr 0x%08" HWADDR_PRIx " value 0x%08" PRIx64 pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR %08x read_count %d returning %d" pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d" pl011_put_fifo_full(void) "FIFO now full, RXFF set"