From patchwork Sat May 6 11:14:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 9714617 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F308D60387 for ; Sat, 6 May 2017 11:21:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD03D28675 for ; Sat, 6 May 2017 11:21:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C0E04285FD; Sat, 6 May 2017 11:21:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7F8DC285FD for ; Sat, 6 May 2017 11:21:23 +0000 (UTC) Received: from localhost ([::1]:50920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6xm6-0007j4-Og for patchwork-qemu-devel@patchwork.kernel.org; Sat, 06 May 2017 07:21:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6xfg-00030Q-4a for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d6xfe-0003vD-RQ for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:44 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:40000) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d6xfe-0003uD-Lw for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:42 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1d6xfd-0008N4-8e; Sat, 06 May 2017 13:14:41 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1d6xfc-0003IF-0D; Sat, 06 May 2017 13:14:40 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 6 May 2017 13:14:27 +0200 Message-Id: <20170506111431.12548-11-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170506111431.12548-1-aurelien@aurel32.net> References: <20170506111431.12548-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 10/14] target/sh4: optimize gen_write_sr using extract op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This doesn't change the generated code on x86, but optimizes it on most RISC architectures and makes the code simpler to read. Signed-off-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sh4/translate.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b4e5606098..8c766eed2a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src) { tcg_gen_andi_i32(cpu_sr, src, ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T))); - tcg_gen_shri_i32(cpu_sr_q, src, SR_Q); - tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1); - tcg_gen_shri_i32(cpu_sr_m, src, SR_M); - tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1); - tcg_gen_shri_i32(cpu_sr_t, src, SR_T); - tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); + tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1); + tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1); + tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1); } static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)