From patchwork Sat May 6 11:14:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 9714609 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3578C60387 for ; Sat, 6 May 2017 11:18:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1246A285FD for ; Sat, 6 May 2017 11:18:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 05F81286B3; Sat, 6 May 2017 11:18:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A6231285FD for ; Sat, 6 May 2017 11:18:49 +0000 (UTC) Received: from localhost ([::1]:50907 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6xjc-0005Y3-Sa for patchwork-qemu-devel@patchwork.kernel.org; Sat, 06 May 2017 07:18:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d6xff-00030L-NJ for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d6xfe-0003v4-Nj for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:43 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:39996) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d6xfe-0003uA-I7 for qemu-devel@nongnu.org; Sat, 06 May 2017 07:14:42 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1d6xfd-0008N0-6n; Sat, 06 May 2017 13:14:41 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1d6xfb-0003Hv-SL; Sat, 06 May 2017 13:14:39 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 6 May 2017 13:14:23 +0200 Message-Id: <20170506111431.12548-7-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170506111431.12548-1-aurelien@aurel32.net> References: <20170506111431.12548-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PATCH v2 06/14] target/sh4: fix BS_EXCP exit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP In case of exception, there is no need to call tcg_gen_exit_tb as the exception helper won't return. Also fix a few cases where BS_BRANCH is called instead of BS_EXCP. Signed-off-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sh4/translate.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 04bc18bf7c..f608e314b6 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -339,7 +339,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \ tcg_gen_movi_i32(cpu_pc, ctx->pc); \ gen_helper_raise_slot_illegal_instruction(cpu_env); \ - ctx->bstate = BS_BRANCH; \ + ctx->bstate = BS_EXCP; \ return; \ } @@ -351,7 +351,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) } else { \ gen_helper_raise_illegal_instruction(cpu_env); \ } \ - ctx->bstate = BS_BRANCH; \ + ctx->bstate = BS_EXCP; \ return; \ } @@ -363,7 +363,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg) } else { \ gen_helper_raise_fpu_disable(cpu_env); \ } \ - ctx->bstate = BS_BRANCH; \ + ctx->bstate = BS_EXCP; \ return; \ } @@ -1289,7 +1289,7 @@ static void _decode_opc(DisasContext * ctx) imm = tcg_const_i32(B7_0); gen_helper_trapa(cpu_env, imm); tcg_temp_free(imm); - ctx->bstate = BS_BRANCH; + ctx->bstate = BS_EXCP; } return; case 0xc800: /* tst #imm,R0 */ @@ -1798,7 +1798,7 @@ static void _decode_opc(DisasContext * ctx) } else { gen_helper_raise_illegal_instruction(cpu_env); } - ctx->bstate = BS_BRANCH; + ctx->bstate = BS_EXCP; } static void decode_opc(DisasContext * ctx) @@ -1867,7 +1867,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) /* We have hit a breakpoint - make sure PC is up-to-date */ tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); - ctx.bstate = BS_BRANCH; + ctx.bstate = BS_EXCP; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -1911,9 +1911,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) gen_goto_tb(&ctx, 0, ctx.pc); break; case BS_EXCP: - /* gen_op_interrupt_restart(); */ - tcg_gen_exit_tb(0); - break; + /* fall through */ case BS_BRANCH: default: break;