| Message ID | 20170508151707.5434-3-rth@twiddle.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 2017-05-08 08:17, Richard Henderson wrote: > From: Miroslav Benes <mbenes@suse.cz> > > Linux arch/s390/kernel/head(64).S uses LPP instruction if it is > available in facilities list provided by stfl/stfle instruction. > This is the case of newer z/System generations and their qemu > definition. > > The description of LPP is at > http://www-01.ibm.com/support/docview.wss?uid=isg26fcd1cc32246f4c8852574ce0044734a > > Signed-off-by: Miroslav Benes <mbenes@suse.cz> > Message-Id: <20170227085353.20787-1-mbenes@suse.cz> > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > target/s390x/insn-data.def | 2 ++ > target/s390x/translate.c | 9 +++++++++ > 2 files changed, 11 insertions(+) Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index b6702da..43c5707 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -845,6 +845,8 @@ /* LOAD CONTROL */ C(0xb700, LCTL, RS_a, Z, 0, a2, 0, 0, lctl, 0) C(0xeb2f, LCTLG, RSY_a, Z, 0, a2, 0, 0, lctlg, 0) +/* LOAD PROGRAM PARAMETER */ + C(0xb280, LPP, S, LPP, 0, m2_64, 0, 0, lpp, 0) /* LOAD PSW */ C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0) /* LOAD PSW EXTENDED */ diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 69940e3..2b66a4e 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1194,6 +1194,7 @@ typedef enum DisasFacility { FAC_SCF, /* store clock fast */ FAC_SFLE, /* store facility list extended */ FAC_ILA, /* interlocked access facility 1 */ + FAC_LPP, /* load-program-parameter */ } DisasFacility; struct DisasInsn { @@ -2567,6 +2568,14 @@ static ExitStatus op_lra(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_lpp(DisasContext *s, DisasOps *o) +{ + check_privileged(s); + + tcg_gen_st_i64(o->in2, cpu_env, offsetof(CPUS390XState, pp)); + return NO_EXIT; +} + static ExitStatus op_lpsw(DisasContext *s, DisasOps *o) { TCGv_i64 t1, t2;