From patchwork Sat May 20 00:26:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 9738419 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E7DE9600C8 for ; Sat, 20 May 2017 00:30:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC40128565 for ; Sat, 20 May 2017 00:30:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD513285AD; Sat, 20 May 2017 00:30:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D95B628565 for ; Sat, 20 May 2017 00:30:12 +0000 (UTC) Received: from localhost ([::1]:60725 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBsHc-0005J5-50 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 19 May 2017 20:30:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58971) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dBsFQ-0004FB-Vh for qemu-devel@nongnu.org; Fri, 19 May 2017 20:27:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dBsFP-0001ae-DJ for qemu-devel@nongnu.org; Fri, 19 May 2017 20:27:56 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:39263) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dBsFK-0001Zu-6b; Fri, 19 May 2017 20:27:50 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 6268520496; Fri, 19 May 2017 20:27:49 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Fri, 19 May 2017 20:27:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=YIMoUu e5kLhsKHBlkpl5uRzviDxg7m1sWa50vwojKuE=; b=UlKSnuhX3APkW9Q3ZCTqcF hnsUlS3LQC/G2YIZjZaAd75ImgGH9aug+mmbgVG1IOG1+0u7WWdFkDxYy3ReX8Ww 9GitJfbZg+wR50aDe8OYehY0AEvyslU45xuW4QtFGa3eycWeuGZMzobqRpW17eRb uf+zrFRsD3ca9T95BSxnAfqGiSytG56hS1YWoJi9G0OlRJTWYhbZvZlj/IwU7X6S cN8C40c7u+CqxpFGut8cK5gc9CQGlk0xDkXYad53zaqr6R4aeMhpOmmGKBlIIwxU mTNxb1Dmfpoh7rvM/k5s2KwKwrWpiHmnCed0nEYU/mkokk827OABB09PXjEX0g7g == DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=YIMoUue5kLhsKHBlkpl5uRzviDxg7m1sWa50vwojK uE=; b=O6qiOH+Iu4FTdYqeNfL7CZjmxEiUIpdoI9IUExaIhZ74CQKYWBjgEQjnd nQs2unvlhHjnAt9eDq16EV3ATQSb0jSSimjW1rW6UC5vjeJxaB06WfFx83+ooLVT JFYZBCxQVIhBeb97wV4EafnObaFxCaw49KuMjibc/0eBg/P4fdS0GRCeLC97/xV9 J1hRW+rPlF/RHYKlFOARKhAbhxqdVxzJPGyWFW9QXyNULyeielIYoR/Sh+35sZtX cGaY4iqn+4nuSNg8JANmYD6Ps96cNhK7Bw1HY6S1bl4gyn1G9eA188EBwvcLgNrf crpdPsc4HLEcDAAJbH+8trlhLws3w== X-ME-Sender: X-Sasl-enc: tfrcbcDKwHnG3uRad3FOQe/73JxlS/TMi1mlTCPlvUDj 1495240068 Received: from keelia.au.ibm.com (unknown [202.90.207.97]) by mail.messagingengine.com (Postfix) with ESMTPA id 7D8CC241E3; Fri, 19 May 2017 20:27:38 -0400 (EDT) From: Andrew Jeffery To: qemu-arm@nongnu.org Date: Sat, 20 May 2017 08:26:52 +0800 Message-Id: <20170520002653.20213-2-andrew@aj.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170520002653.20213-1-andrew@aj.id.au> References: <20170520002653.20213-1-andrew@aj.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH 1/2] hw/adc: Add basic Aspeed ADC model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Ryan Chen , Andrew Jeffery , Alistair Francis , qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Joel Stanley Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This model implements enough behaviour to do basic functionality tests such as device initialisation and read out of dummy sample values. The sample value generation strategy is similar to the STM ADC already in the tree. Signed-off-by: Andrew Jeffery --- hw/adc/Makefile.objs | 1 + hw/adc/aspeed_adc.c | 246 ++++++++++++++++++++++++++++++++++++++++++++ include/hw/adc/aspeed_adc.h | 33 ++++++ 3 files changed, 280 insertions(+) create mode 100644 hw/adc/aspeed_adc.c create mode 100644 include/hw/adc/aspeed_adc.h diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs index 3f6dfdedaec7..2bf9362ba3c4 100644 --- a/hw/adc/Makefile.objs +++ b/hw/adc/Makefile.objs @@ -1 +1,2 @@ obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o +obj-$(CONFIG_ASPEED_SOC) += aspeed_adc.o diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c new file mode 100644 index 000000000000..d08f1684f7bc --- /dev/null +++ b/hw/adc/aspeed_adc.c @@ -0,0 +1,246 @@ +/* + * Aspeed ADC + * + * Andrew Jeffery + * + * Copyright 2017 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/adc/aspeed_adc.h" +#include "qapi/error.h" +#include "qemu/log.h" + +#define ASPEED_ADC_ENGINE_CTRL 0x00 +#define ASPEED_ADC_ENGINE_CH_EN_MASK 0xffff0000 +#define ASPEED_ADC_ENGINE_CH_EN(x) ((BIT(x)) << 16) +#define ASPEED_ADC_ENGINE_INIT BIT(8) +#define ASPEED_ADC_ENGINE_AUTO_COMP BIT(5) +#define ASPEED_ADC_ENGINE_COMP BIT(4) +#define ASPEED_ADC_ENGINE_MODE_MASK 0x0000000e +#define ASPEED_ADC_ENGINE_MODE_OFF (0b000 << 1) +#define ASPEED_ADC_ENGINE_MODE_STANDBY (0b001 << 1) +#define ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1) +#define ASPEED_ADC_ENGINE_EN BIT(0) + +#define ASPEED_ADC_L_MASK ((1 << 10) - 1) +#define ASPEED_ADC_L(x) ((x) & ASPEED_ADC_L_MASK) +#define ASPEED_ADC_H(x) (((x) >> 16) & ASPEED_ADC_L_MASK) +#define ASPEED_ADC_LH_MASK (ASPEED_ADC_L_MASK << 16 | ASPEED_ADC_L_MASK) + +static inline uint32_t update_channels(uint32_t current) +{ + const uint32_t next = (current + 7) & 0x3ff; + + return (next << 16) | next; +} + +static bool breaks_threshold(AspeedADCState *s, int ch_off) +{ + const uint32_t a = ASPEED_ADC_L(s->channels[ch_off]); + const uint32_t a_lower = ASPEED_ADC_L(s->bounds[2 * ch_off]); + const uint32_t a_upper = ASPEED_ADC_H(s->bounds[2 * ch_off]); + const uint32_t b = ASPEED_ADC_H(s->channels[ch_off]); + const uint32_t b_lower = ASPEED_ADC_L(s->bounds[2 * ch_off + 1]); + const uint32_t b_upper = ASPEED_ADC_H(s->bounds[2 * ch_off + 1]); + + return ((a < a_lower || a > a_upper)) || + ((b < b_lower || b > b_upper)); +} + +static uint32_t read_channel_sample(AspeedADCState *s, int ch_off) +{ + uint32_t ret; + + /* Poor man's sampling */ + ret = s->channels[ch_off]; + s->channels[ch_off] = update_channels(s->channels[ch_off]); + + if (breaks_threshold(s, ch_off)) { + qemu_irq_raise(s->irq); + } + + return ret; +} + +#define TO_INDEX(addr, base) (((addr) - (base)) >> 2) + +static uint64_t aspeed_adc_read(void *opaque, hwaddr addr, + unsigned int size) +{ + AspeedADCState *s = ASPEED_ADC(opaque); + uint64_t ret; + + switch (addr) { + case 0x00: + ret = s->engine_ctrl; + break; + case 0x04: + ret = s->irq_ctrl; + break; + case 0x08: + ret = s->vga_detect_ctrl; + break; + case 0x0c: + ret = s->adc_clk_ctrl; + break; + case 0x10 ... 0x2e: + ret = read_channel_sample(s, TO_INDEX(addr, 0x10)); + break; + case 0x30 ... 0x6e: + ret = s->bounds[TO_INDEX(addr, 0x30)]; + break; + case 0x70 ... 0xae: + ret = s->hysteresis[TO_INDEX(addr, 0x70)]; + break; + case 0xc0: + ret = s->irq_src; + break; + case 0xc4: + ret = s->comp_trim; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: addr: 0x%lx, size: %u\n", __func__, addr, + size); + ret = 0; + break; + } + + return ret; +} + +static void aspeed_adc_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + AspeedADCState *s = ASPEED_ADC(opaque); + + switch (addr) { + case 0x00: + { + uint32_t init; + + init = !!(val & ASPEED_ADC_ENGINE_EN); + init *= ASPEED_ADC_ENGINE_INIT; + + val &= ~ASPEED_ADC_ENGINE_INIT; + val |= init; + } + + val &= ~ASPEED_ADC_ENGINE_AUTO_COMP; + s->engine_ctrl = val; + + break; + case 0x04: + s->irq_ctrl = val; + break; + case 0x08: + s->vga_detect_ctrl = val; + break; + case 0x0c: + s->adc_clk_ctrl = val; + break; + case 0x10 ... 0x2e: + s->channels[TO_INDEX(addr, 0x10)] = val; + break; + case 0x30 ... 0x6e: + s->bounds[TO_INDEX(addr, 0x30)] = (val & ASPEED_ADC_LH_MASK); + break; + case 0x70 ... 0xae: + s->hysteresis[TO_INDEX(addr, 0x70)] = + (val & (BIT(31) | ASPEED_ADC_LH_MASK)); + break; + case 0xc0: + s->irq_src = (val & 0xffff); + break; + case 0xc4: + s->comp_trim = (val & 0xf); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: %lu\n", __func__, addr); + break; + } +} + +static const MemoryRegionOps aspeed_adc_ops = { + .read = aspeed_adc_read, + .write = aspeed_adc_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid.min_access_size = 4, + .valid.max_access_size = 4, + .valid.unaligned = false, +}; + +static void aspeed_adc_reset(DeviceState *dev) +{ + struct AspeedADCState *s = ASPEED_ADC(dev); + + s->engine_ctrl = 0; + s->irq_ctrl = 0; + s->vga_detect_ctrl = 0x0000000f; + s->adc_clk_ctrl = 0x0000000f; + memset(s->channels, 0, sizeof(s->channels)); + memset(s->bounds, 0, sizeof(s->bounds)); + memset(s->hysteresis, 0, sizeof(s->hysteresis)); + s->irq_src = 0; + s->comp_trim = 0; +} + +static void aspeed_adc_realize(DeviceState *dev, Error **errp) +{ + AspeedADCState *s = ASPEED_ADC(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_adc_ops, s, + TYPE_ASPEED_ADC, 0x1000); + + sysbus_init_mmio(sbd, &s->mmio); +} + +static const VMStateDescription vmstate_aspeed_adc = { + .name = TYPE_ASPEED_ADC, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(engine_ctrl, AspeedADCState), + VMSTATE_UINT32(irq_ctrl, AspeedADCState), + VMSTATE_UINT32(vga_detect_ctrl, AspeedADCState), + VMSTATE_UINT32(adc_clk_ctrl, AspeedADCState), + VMSTATE_UINT32_ARRAY(channels, AspeedADCState, + ASPEED_ADC_NR_CHANNELS / 2), + VMSTATE_UINT32_ARRAY(bounds, AspeedADCState, ASPEED_ADC_NR_CHANNELS), + VMSTATE_UINT32_ARRAY(hysteresis, AspeedADCState, + ASPEED_ADC_NR_CHANNELS), + VMSTATE_UINT32(irq_src, AspeedADCState), + VMSTATE_UINT32(comp_trim, AspeedADCState), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_adc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = aspeed_adc_realize; + dc->reset = aspeed_adc_reset; + dc->desc = "Aspeed Analog-to-Digital Converter", + dc->vmsd = &vmstate_aspeed_adc; +} + +static const TypeInfo aspeed_adc_info = { + .name = TYPE_ASPEED_ADC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedADCState), + .class_init = aspeed_adc_class_init, +}; + +static void aspeed_adc_register_types(void) +{ + type_register_static(&aspeed_adc_info); +} + +type_init(aspeed_adc_register_types); diff --git a/include/hw/adc/aspeed_adc.h b/include/hw/adc/aspeed_adc.h new file mode 100644 index 000000000000..ae2089ac62ca --- /dev/null +++ b/include/hw/adc/aspeed_adc.h @@ -0,0 +1,33 @@ +#ifndef _ASPEED_ADC_H_ +#define _ASPEED_ADC_H_ + +#include + +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/sysbus.h" + +#define TYPE_ASPEED_ADC "aspeed.adc" +#define ASPEED_ADC(obj) OBJECT_CHECK(AspeedADCState, (obj), TYPE_ASPEED_ADC) + +#define ASPEED_ADC_NR_CHANNELS 16 + +typedef struct AspeedADCState { + /* */ + SysBusDevice parent; + + MemoryRegion mmio; + qemu_irq irq; + + uint32_t engine_ctrl; + uint32_t irq_ctrl; + uint32_t vga_detect_ctrl; + uint32_t adc_clk_ctrl; + uint32_t channels[ASPEED_ADC_NR_CHANNELS / 2]; + uint32_t bounds[ASPEED_ADC_NR_CHANNELS]; + uint32_t hysteresis[ASPEED_ADC_NR_CHANNELS]; + uint32_t irq_src; + uint32_t comp_trim; +} AspeedADCState; + +#endif /* _ASPEED_ADC_H_ */