From patchwork Wed May 24 22:08:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9747151 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2574E60246 for ; Wed, 24 May 2017 22:11:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1638526E4E for ; Wed, 24 May 2017 22:11:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0A51426E56; Wed, 24 May 2017 22:11:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5093D26E4E for ; Wed, 24 May 2017 22:11:30 +0000 (UTC) Received: from localhost ([::1]:57035 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeV7-000178-Uo for patchwork-qemu-devel@patchwork.kernel.org; Wed, 24 May 2017 18:11:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dDeSP-0007gU-3B for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dDeSN-00059h-To for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:41 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:33354) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dDeSN-00059V-OW for qemu-devel@nongnu.org; Wed, 24 May 2017 18:08:39 -0400 Received: by mail-qt0-x244.google.com with SMTP id a46so28076333qte.0 for ; Wed, 24 May 2017 15:08:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=10kBqtvYA3p+2fUWkIT0DQhdw93yxtXRcMkzzIh8YuQ=; b=n7p5ZeSFwlXyaJbDgtIX1eMRvuxeQrwPjzdz3X4nKU2olzWSo97+7mjGh/ioyxBWa7 n3zUL8MowuqEvWKBky5sW3GIU+VdnMMBYAoOgRk4sMjeRbfQUfMmH70z9pd3Qc2fpZHJ tmwGK33ajzU/T0OirA9u70ltMfeF4rtAMCSkK4p7Zav5y8QXWJnf6AeyouP9l4UN18ol DzowYgTDFvOn9f3cNeIsVsH26Vj/9IAoBpJZRF+v3o4RpQzadkqWsUgYjGf/OR5qY+YQ eHarFTRgE1ZT4YclVHo2PUhpUasb+JflM5mCzix7dQwXkRiFJFjJFqVup6ZrX4Dmkkwl bIJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=10kBqtvYA3p+2fUWkIT0DQhdw93yxtXRcMkzzIh8YuQ=; b=Fc4PyBQlsh5KyGucfMUldpLx02iPwP3nQUVTafh22G+ppjLvL3aQpo4kJYs9HF9WkG WX8kRuVoMF9xMBJFV89G03zXjyPB5fYQP2QkF5BlsAHRxP4XGTFkRowcyGUUZutGaHN1 aYrWlhEFT8veh02NC/IQLwls9+rAl46rJicPxZSf/puMqJpermw3ddKbcKzxTtTUIpBo wYsPbMHQEnUMJkpZ6DidEXxIHqIkv4FqraK8Hnsl1L+ajdjffRZQ9aPOyZ+smxEGkT7v ybG+v0H9U/NzgNXEb8viRwPUOzJMvA2twtVr6f9Vd/u9hcW9HmgaX4NJ4ctWB5t2qYmh tJVQ== X-Gm-Message-State: AODbwcBUCt61LwortfG1ovP1r0u8Oe1blL13QAUcj6Fyk8YednKm+QQI mShJizaiEFHI2oICOYU= X-Received: by 10.237.37.154 with SMTP id x26mr39654140qtc.133.1495663719041; Wed, 24 May 2017 15:08:39 -0700 (PDT) Received: from bigtime.twiddle.net.com ([2602:47:d954:1500:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id y188sm3347693qkb.49.2017.05.24.15.08.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 May 2017 15:08:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 24 May 2017 15:08:27 -0700 Message-Id: <20170524220827.21154-5-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170524220827.21154-1-rth@twiddle.net> References: <20170524220827.21154-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH 4/4] target/s390x: Re-implement a few EXECUTE target insns directly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP While the previous patch is required for proper conformance, the vast majority of target insns are MVC and XC for implementing memmove and memset respectively. The next most common are CLC, TR, and SVC. Implementing these (and a few others for which we already have an implementation) directly is faster than going through full translation to a TB. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/s390x/mem_helper.c | 66 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 51 insertions(+), 15 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 3a77edc..e35571e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -200,31 +200,30 @@ uint32_t HELPER(oc)(CPUS390XState *env, uint32_t l, uint64_t dest, } /* memmove */ -static void do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t dest, - uint64_t src, uintptr_t ra) +static uint32_t do_helper_mvc(CPUS390XState *env, uint32_t l, uint64_t dest, + uint64_t src, uintptr_t ra) { uint32_t i; HELPER_LOG("%s l %d dest %" PRIx64 " src %" PRIx64 "\n", __func__, l, dest, src); + /* mvc and memmove do not behave the same when areas overlap! */ /* mvc with source pointing to the byte after the destination is the same as memset with the first source byte */ if (dest == src + 1) { fast_memset(env, dest, cpu_ldub_data_ra(env, src, ra), l + 1, ra); - return; - } - - /* mvc and memmove do not behave the same when areas overlap! */ - if (dest < src || src + l < dest) { + } else if (dest < src || src + l < dest) { fast_memmove(env, dest, src, l + 1, ra); - return; + } else { + /* slow version with byte accesses which always work */ + for (i = 0; i <= l; i++) { + uint8_t x = cpu_ldub_data_ra(env, src + i, ra); + cpu_stb_data_ra(env, dest + i, x, ra); + } } - /* slow version with byte accesses which always work */ - for (i = 0; i <= l; i++) { - cpu_stb_data_ra(env, dest + i, cpu_ldub_data_ra(env, src + i, ra), ra); - } + return env->cc_op; } void HELPER(mvc)(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) @@ -692,8 +691,8 @@ void HELPER(unpk)(CPUS390XState *env, uint32_t len, uint64_t dest, } } -static void do_helper_tr(CPUS390XState *env, uint32_t len, uint64_t array, - uint64_t trans, uintptr_t ra) +static uint32_t do_helper_tr(CPUS390XState *env, uint32_t len, uint64_t array, + uint64_t trans, uintptr_t ra) { uint32_t i; @@ -702,12 +701,14 @@ static void do_helper_tr(CPUS390XState *env, uint32_t len, uint64_t array, uint8_t new_byte = cpu_ldub_data_ra(env, trans + byte, ra); cpu_stb_data_ra(env, array + i, new_byte, ra); } + + return env->cc_op; } void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array, uint64_t trans) { - return do_helper_tr(env, len, array, trans, GETPC()); + do_helper_tr(env, len, array, trans, GETPC()); } uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, @@ -1221,6 +1222,41 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) g_assert_not_reached(); } + /* The very most common cases can be sped up by avoiding a new TB. */ + if ((opc & 0xf0) == 0xd0) { + typedef uint32_t (*dx_helper)(CPUS390XState *, uint32_t, uint64_t, + uint64_t, uintptr_t); + static const dx_helper dx[16] = { + [0x2] = do_helper_mvc, + [0x4] = do_helper_nc, + [0x5] = do_helper_clc, + [0x6] = do_helper_oc, + [0x7] = do_helper_xc, + [0xc] = do_helper_tr, + [0xd] = do_helper_trt, + }; + dx_helper helper = dx[opc & 0xf]; + + if (helper) { + uint32_t l = extract64(insn, 48, 8); + uint32_t b1 = extract64(insn, 44, 4); + uint32_t d1 = extract64(insn, 32, 12); + uint32_t b2 = extract64(insn, 28, 4); + uint32_t d2 = extract64(insn, 16, 12); + uint64_t a1 = get_address(env, 0, b1, d1); + uint64_t a2 = get_address(env, 0, b2, d2); + + env->cc_op = helper(env, l, a1, a2, 0); + env->psw.addr += ilen; + return; + } + } else if (opc == 0x0a) { + env->int_svc_code = extract64(insn, 48, 8); + env->int_svc_ilen = ilen; + helper_exception(env, EXCP_SVC); + g_assert_not_reached(); + } + /* Record the insn we want to execute as well as the ilen to use during the execution of the target insn. This will also ensure that ex_value is non-zero, which flags that we are in a state