From patchwork Tue May 30 19:15:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 9755171 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0D07E602BF for ; Tue, 30 May 2017 19:17:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01F8B26B39 for ; Tue, 30 May 2017 19:17:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EAC0927F10; Tue, 30 May 2017 19:17:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6E50E27E5A for ; Tue, 30 May 2017 19:17:15 +0000 (UTC) Received: from localhost ([::1]:55877 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFmdm-0005aG-9p for patchwork-qemu-devel@patchwork.kernel.org; Tue, 30 May 2017 15:17:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFmcc-0005Zm-Lb for qemu-devel@nongnu.org; Tue, 30 May 2017 15:16:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFmcb-0007fi-II for qemu-devel@nongnu.org; Tue, 30 May 2017 15:16:02 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:52278) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFmcb-0007em-Ba for qemu-devel@nongnu.org; Tue, 30 May 2017 15:16:01 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dFmcZ-00028N-DC; Tue, 30 May 2017 21:15:59 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dFmcX-0008Dr-LV; Tue, 30 May 2017 21:15:57 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 21:15:50 +0200 Message-Id: <20170530191553.31500-3-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170530191553.31500-1-aurelien@aurel32.net> References: <20170530191553.31500-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL v2 2/5] target/sh4: fix reset when using a kernel and an initrd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , stefanha@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP When a masked exception happens, the SH4 CPU generates a non-masked reset exception, which then jumps to the reset vector at address 0xA0000000. While this is emulated correctly in QEMU, this does not work when using a kernel and initrd as this address then contain an illegal instruction (and there is no guarantee the kernel and initrd haven't been overwritten). Therefore call qemu_system_reset_request to reload the kernel and initrd and load the program counter to the kernel entry point. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target/sh4/helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 4c024f9529..16fcd1bbf2 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/log.h" +#include "sysemu/sysemu.h" #if !defined(CONFIG_USER_ONLY) #include "hw/sh4/sh_intc.h" @@ -92,7 +93,14 @@ void superh_cpu_do_interrupt(CPUState *cs) if (env->sr & (1u << SR_BL)) { if (do_exp && cs->exception_index != 0x1e0) { - cs->exception_index = 0x000; /* masked exception -> reset */ + /* In theory a masked exception generates a reset exception, + which in turn jumps to the reset vector. However this only + works when using a bootloader. When using a kernel and an + initrd, they need to be reloaded and the program counter + should be loaded with the kernel entry point. + qemu_system_reset_request takes care of that. */ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; } if (do_irq && !env->in_sleep) { return; /* masked */