From patchwork Tue May 30 19:15:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 9755173 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2A633602BF for ; Tue, 30 May 2017 19:17:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F3B026B39 for ; Tue, 30 May 2017 19:17:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1420027F10; Tue, 30 May 2017 19:17:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B54D827E5A for ; Tue, 30 May 2017 19:17:17 +0000 (UTC) Received: from localhost ([::1]:55878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFmdo-0005ba-NI for patchwork-qemu-devel@patchwork.kernel.org; Tue, 30 May 2017 15:17:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFmcc-0005Zl-H5 for qemu-devel@nongnu.org; Tue, 30 May 2017 15:16:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFmcb-0007fT-H1 for qemu-devel@nongnu.org; Tue, 30 May 2017 15:16:02 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:52284) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dFmcb-0007en-BI for qemu-devel@nongnu.org; Tue, 30 May 2017 15:16:01 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dFmcZ-00028P-D9; Tue, 30 May 2017 21:15:59 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dFmcX-0008E5-R0; Tue, 30 May 2017 21:15:57 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 21:15:52 +0200 Message-Id: <20170530191553.31500-5-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170530191553.31500-1-aurelien@aurel32.net> References: <20170530191553.31500-1-aurelien@aurel32.net> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL v2 4/5] target/sh4: ignore interrupts in a delay slot X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , stefanha@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Delay slots are indivisible, therefore avoid scheduling an interrupt in the delay slot. However exceptions are possible. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target/sh4/helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5785d6d22a..28d93c2543 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -871,8 +871,16 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { - superh_cpu_do_interrupt(cs); - return true; + SuperHCPU *cpu = SUPERH_CPU(cs); + CPUSH4State *env = &cpu->env; + + /* Delay slots are indivisible, ignore interrupts */ + if (env->flags & DELAY_SLOT_MASK) { + return false; + } else { + superh_cpu_do_interrupt(cs); + return true; + } } return false; }