From patchwork Thu Jun 1 10:14:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 9759145 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC37C60375 for ; Thu, 1 Jun 2017 10:15:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8999327F17 for ; Thu, 1 Jun 2017 10:15:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7DC26283BF; Thu, 1 Jun 2017 10:15:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C66C327F17 for ; Thu, 1 Jun 2017 10:15:22 +0000 (UTC) Received: from localhost ([::1]:42598 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGN8T-0003XU-WF for patchwork-qemu-devel@patchwork.kernel.org; Thu, 01 Jun 2017 06:15:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dGN7x-0003XH-QN for qemu-devel@nongnu.org; Thu, 01 Jun 2017 06:14:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dGN7u-0002Cd-J6 for qemu-devel@nongnu.org; Thu, 01 Jun 2017 06:14:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45147) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dGN7u-0002B3-Ak for qemu-devel@nongnu.org; Thu, 01 Jun 2017 06:14:46 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F348E800AE; Thu, 1 Jun 2017 10:14:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com F348E800AE Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=david@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com F348E800AE Received: from t460s.redhat.com (ovpn-117-250.ams2.redhat.com [10.36.117.250]) by smtp.corp.redhat.com (Postfix) with ESMTP id 367841751E; Thu, 1 Jun 2017 10:14:40 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Thu, 1 Jun 2017 12:14:38 +0200 Message-Id: <20170601101438.28732-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Thu, 01 Jun 2017 10:14:45 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v1] s390x/cpumodel: wire up cpu type + id for TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, david@redhat.com, agraf@suse.de, Aurelien Jarno , rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Let's properly expose the CPU type (machine-type number) via "STORE CPU ID" and "STORE SUBSYSTEM INFORMATION". As TCG emulates basic mode, the CPU identification number has the format "Annnnn", whereby A is the CPU address, and n are parts of the CPU serial number (0 for us for now). Signed-off-by: David Hildenbrand --- Tested stidp with a kvm-unit-test that is still being worked on (waiting for Thomas' interception test to integrate). I think we are missing quite some "operand alignment checks" in other handlers, too. --- target/s390x/cpu.h | 1 - target/s390x/cpu_models.c | 2 -- target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 +- target/s390x/misc_helper.c | 26 +++++++++++++++++++++++--- target/s390x/translate.c | 11 ++++------- 6 files changed, 29 insertions(+), 14 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index c74b419..02bd8bf 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -147,7 +147,6 @@ typedef struct CPUS390XState { CPU_COMMON uint32_t cpu_num; - uint32_t machine_type; uint64_t tod_offset; uint64_t tod_basetime; diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index b6220c8..99ec0c8 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -710,8 +710,6 @@ static inline void apply_cpu_model(const S390CPUModel *model, Error **errp) if (kvm_enabled()) { kvm_s390_apply_cpu_model(model, errp); - } else if (model) { - /* FIXME TCG - use data for stdip/stfl */ } if (!*errp) { diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 0b70770..0c8f745 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -121,6 +121,7 @@ DEF_HELPER_FLAGS_3(sturg, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_1(per_check_exception, void, env) DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_RWG, void, env, i64, i64) DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_RWG, void, env, i64) +DEF_HELPER_2(stidp, void, env, i64) DEF_HELPER_2(xsch, void, env, i64) DEF_HELPER_2(csch, void, env, i64) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 55a7c52..83e7d01 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -902,7 +902,7 @@ /* STORE CPU ADDRESS */ C(0xb212, STAP, S, Z, la2, 0, new, m1_16, stap, 0) /* STORE CPU ID */ - C(0xb202, STIDP, S, Z, la2, 0, new, m1_64, stidp, 0) + C(0xb202, STIDP, S, Z, 0, a2, 0, 0, stidp, 0) /* STORE CPU TIMER */ C(0xb209, STPT, S, Z, la2, 0, new, m1_64, stpt, 0) /* STORE FACILITY LIST */ diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 1b9f448..f682511 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -383,6 +383,7 @@ uint64_t HELPER(stpt)(CPUS390XState *env) uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1) { + S390CPU *cpu = s390_env_get_cpu(env); int cc = 0; int sel1, sel2; @@ -402,12 +403,14 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, if ((sel1 == 1) && (sel2 == 1)) { /* Basic Machine Configuration */ struct sysib_111 sysib; + char type[5] = {}; memset(&sysib, 0, sizeof(sysib)); ebcdic_put(sysib.manuf, "QEMU ", 16); - /* same as machine type number in STORE CPU ID */ - ebcdic_put(sysib.type, "QEMU", 4); - /* same as model number in STORE CPU ID */ + /* same as machine type number in STORE CPU ID, but in EBCDIC */ + snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type); + ebcdic_put(sysib.type, type, 4); + /* model number (not stored in STORE CPU ID for z/Architecure) */ ebcdic_put(sysib.model, "QEMU ", 16); ebcdic_put(sysib.sequence, "QEMU ", 16); ebcdic_put(sysib.plant, "QEMU", 4); @@ -736,3 +739,20 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t addr) env->regs[0] = deposit64(env->regs[0], 0, 8, max_m1); return (count_m1 >= max_m1 ? 0 : 3); } + +#ifndef CONFIG_USER_ONLY +void HELPER(stidp)(CPUS390XState *env, uint64_t addr) +{ + S390CPU *cpu = s390_env_get_cpu(env); + uint64_t cpuid = s390_cpuid_from_cpu_model(cpu->model); + + if (addr & 0x7) { + program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC); + return; + } + + /* basic mode, write the cpu address into the first 4 bit of the ID */ + cpuid |= ((uint64_t)env->cpu_num & 0xf) << 54; + cpu_stq_data(env, addr, cpuid); +} +#endif diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4c48c59..1a99093 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3646,18 +3646,15 @@ static ExitStatus op_stctl(DisasContext *s, DisasOps *o) return NO_EXIT; } +#ifndef CONFIG_USER_ONLY static ExitStatus op_stidp(DisasContext *s, DisasOps *o) { - TCGv_i64 t1 = tcg_temp_new_i64(); - check_privileged(s); - tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num)); - tcg_gen_ld32u_i64(t1, cpu_env, offsetof(CPUS390XState, machine_type)); - tcg_gen_deposit_i64(o->out, o->out, t1, 32, 32); - tcg_temp_free_i64(t1); - + potential_page_fault(s); + gen_helper_stidp(cpu_env, o->in2); return NO_EXIT; } +#endif static ExitStatus op_spt(DisasContext *s, DisasOps *o) {