From patchwork Fri Jun 9 13:34:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 9778463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F0B7F60350 for ; Fri, 9 Jun 2017 13:36:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE7FC2861E for ; Fri, 9 Jun 2017 13:36:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D34BF28628; Fri, 9 Jun 2017 13:36:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 553592861E for ; Fri, 9 Jun 2017 13:36:58 +0000 (UTC) Received: from localhost ([::1]:54725 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJK5x-0001Wc-Ez for patchwork-qemu-devel@patchwork.kernel.org; Fri, 09 Jun 2017 09:36:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33716) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJK3l-0000fg-6K for qemu-devel@nongnu.org; Fri, 09 Jun 2017 09:34:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJK3g-0006na-1S for qemu-devel@nongnu.org; Fri, 09 Jun 2017 09:34:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49766) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dJK3f-0006nS-PI for qemu-devel@nongnu.org; Fri, 09 Jun 2017 09:34:35 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B689B20B1C; Fri, 9 Jun 2017 13:34:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com B689B20B1C Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=david@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com B689B20B1C Received: from t460s.redhat.com (unknown [10.36.118.17]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3C4AA8906D; Fri, 9 Jun 2017 13:34:33 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Fri, 9 Jun 2017 15:34:26 +0200 Message-Id: <20170609133426.11447-3-david@redhat.com> In-Reply-To: <20170609133426.11447-1-david@redhat.com> References: <20170609133426.11447-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Fri, 09 Jun 2017 13:34:34 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/2] s390x/cpumodel: wire up cpu type + id for TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, david@redhat.com, agraf@suse.de, Aurelien Jarno , rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Let's properly expose the CPU type (machine-type number) via "STORE CPU ID" and "STORE SUBSYSTEM INFORMATION". As TCG emulates basic mode, the CPU identification number has the format "Annnnn", whereby A is the CPU address, and n are parts of the CPU serial number (0 for us for now). A specification exception will be injected if the address is not aligned to a double word. Low address protection will not be checked as we're missing some more general support for that. Signed-off-by: David Hildenbrand --- target/s390x/cpu.h | 2 +- target/s390x/cpu_models.c | 8 ++++++-- target/s390x/insn-data.def | 2 +- target/s390x/misc_helper.c | 9 ++++++--- target/s390x/translate.c | 9 ++------- 5 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a4d31df..502d3d7 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -149,7 +149,7 @@ typedef struct CPUS390XState { CPU_COMMON uint32_t cpu_num; - uint32_t machine_type; + uint64_t cpuid; uint64_t tod_offset; uint64_t tod_basetime; diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index b34318f..c508ae1 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -737,8 +737,6 @@ static inline void apply_cpu_model(const S390CPUModel *model, Error **errp) if (kvm_enabled()) { kvm_s390_apply_cpu_model(model, errp); - } else if (model) { - /* FIXME TCG - use data for stdip/stfl */ } if (!*errp) { @@ -786,6 +784,12 @@ void s390_realize_cpu_model(CPUState *cs, Error **errp) } apply_cpu_model(cpu->model, errp); + + cpu->env.cpuid = s390_cpuid_from_cpu_model(cpu->model); + if (tcg_enabled()) { + /* basic mode, write the cpu address into the first 4 bit of the ID */ + cpu->env.cpuid |= ((uint64_t)cpu->env.cpu_num & 0xf) << 54; + } } static void get_feature(Object *obj, Visitor *v, const char *name, diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 73dd05d..d089707 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -960,7 +960,7 @@ /* STORE CPU ADDRESS */ C(0xb212, STAP, S, Z, la2, 0, new, m1_16, stap, 0) /* STORE CPU ID */ - C(0xb202, STIDP, S, Z, la2, 0, new, m1_64, stidp, 0) + C(0xb202, STIDP, S, Z, la2, 0, new, 0, stidp, 0) /* STORE CPU TIMER */ C(0xb209, STPT, S, Z, la2, 0, new, m1_64, stpt, 0) /* STORE FACILITY LIST */ diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index edcdf17..75fd13e 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -383,6 +383,7 @@ uint64_t HELPER(stpt)(CPUS390XState *env) uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1) { + S390CPU *cpu = s390_env_get_cpu(env); int cc = 0; int sel1, sel2; @@ -402,12 +403,14 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, if ((sel1 == 1) && (sel2 == 1)) { /* Basic Machine Configuration */ struct sysib_111 sysib; + char type[5] = {}; memset(&sysib, 0, sizeof(sysib)); ebcdic_put(sysib.manuf, "QEMU ", 16); - /* same as machine type number in STORE CPU ID */ - ebcdic_put(sysib.type, "QEMU", 4); - /* same as model number in STORE CPU ID */ + /* same as machine type number in STORE CPU ID, but in EBCDIC */ + snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type); + ebcdic_put(sysib.type, type, 4); + /* model number (not stored in STORE CPU ID for z/Architecure) */ ebcdic_put(sysib.model, "QEMU ", 16); ebcdic_put(sysib.sequence, "QEMU ", 16); ebcdic_put(sysib.plant, "QEMU", 4); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 95f91d4..2f182cc 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3877,14 +3877,9 @@ static ExitStatus op_stctl(DisasContext *s, DisasOps *o) static ExitStatus op_stidp(DisasContext *s, DisasOps *o) { - TCGv_i64 t1 = tcg_temp_new_i64(); - check_privileged(s); - tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num)); - tcg_gen_ld32u_i64(t1, cpu_env, offsetof(CPUS390XState, machine_type)); - tcg_gen_deposit_i64(o->out, o->out, t1, 32, 32); - tcg_temp_free_i64(t1); - + tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, cpuid)); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEQ | MO_ALIGN); return NO_EXIT; }