From patchwork Thu Jun 22 09:41:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 9803863 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A1CCB600C5 for ; Thu, 22 Jun 2017 09:44:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91AFE285D1 for ; Thu, 22 Jun 2017 09:44:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 86341285E8; Thu, 22 Jun 2017 09:44:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 049A0285D1 for ; Thu, 22 Jun 2017 09:44:41 +0000 (UTC) Received: from localhost ([::1]:57920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dNyfI-0001Yr-8r for patchwork-qemu-devel@patchwork.kernel.org; Thu, 22 Jun 2017 05:44:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dNycs-0000Iz-7p for qemu-devel@nongnu.org; Thu, 22 Jun 2017 05:42:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dNycr-0000b2-2t for qemu-devel@nongnu.org; Thu, 22 Jun 2017 05:42:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42262) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dNycq-0000aX-QX for qemu-devel@nongnu.org; Thu, 22 Jun 2017 05:42:09 -0400 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id ACD51C00C113; Thu, 22 Jun 2017 09:42:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com ACD51C00C113 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=david@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com ACD51C00C113 Received: from t460s.redhat.com (ovpn-117-93.ams2.redhat.com [10.36.117.93]) by smtp.corp.redhat.com (Postfix) with ESMTP id 352C16EE2C; Thu, 22 Jun 2017 09:42:04 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Thu, 22 Jun 2017 11:41:51 +0200 Message-Id: <20170622094151.28633-4-david@redhat.com> In-Reply-To: <20170622094151.28633-1-david@redhat.com> References: <20170622094151.28633-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 22 Jun 2017 09:42:07 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 3/3] target/s390x: Implement idte instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, david@redhat.com, agraf@suse.de, Aurelien Jarno , rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Let's keep it very simple for now and flush the complete tlb, we currently can't find the right entries in our tlb, we would have to store the used tables for each element. As we now fully implement the DAT-enhancement facility, we can allow to enable it for the qemu CPU model. Signed-off-by: David Hildenbrand --- target/s390x/cpu_models.c | 1 + target/s390x/helper.h | 1 + target/s390x/insn-data.def | 2 ++ target/s390x/mem_helper.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++ target/s390x/translate.c | 15 ++++++++++++++ 5 files changed, 70 insertions(+) diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 8fce957..74e3369 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -675,6 +675,7 @@ static void check_compatibility(const S390CPUModel *max_model, static void add_qemu_cpu_model_features(S390FeatBitmap fbm) { static const int feats[] = { + S390_FEAT_DAT_ENH, S390_FEAT_STFLE, S390_FEAT_EXTENDED_IMMEDIATE, S390_FEAT_EXTENDED_TRANSLATION_2, diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 69249a5..d219ae4 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -130,6 +130,7 @@ DEF_HELPER_4(mvcs, i32, env, i64, i64, i64) DEF_HELPER_4(mvcp, i32, env, i64, i64, i64) DEF_HELPER_4(sigp, i32, env, i64, i32, i64) DEF_HELPER_FLAGS_2(sacf, TCG_CALL_NO_WG, void, env, i64) +DEF_HELPER_FLAGS_4(idte, TCG_CALL_NO_RWG, void, env, i64, i64, i32) DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32) DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index d089707..82c5d53 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -900,6 +900,8 @@ C(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0) /* INSERT STORAGE KEY EXTENDED */ C(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0) +/* INVALIDATE DAT TABLE ENTRY */ + C(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0) /* INVALIDATE PAGE TABLE ENTRY */ C(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0) /* LOAD CONTROL */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 1507175..6224da5 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1539,6 +1539,57 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2) return cc; } +void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4) +{ + CPUState *cs = CPU(s390_env_get_cpu(env)); + const uintptr_t ra = GETPC(); + uint64_t table, entry, raddr; + uint16_t entries, i, index = 0; + + if (r2 & 0xff000) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIFICATION, 4); + } + + if (!(r2 & 0x800)) { + /* invalidation-and-clearing operation */ + table = r1 & _ASCE_ORIGIN; + entries = (r2 & 0x7ff) + 1; + + switch (r1 & _ASCE_TYPE_MASK) { + case _ASCE_TYPE_REGION1: + index = (r2 >> 53) & 0x7ff; + break; + case _ASCE_TYPE_REGION2: + index = (r2 >> 42) & 0x7ff; + break; + case _ASCE_TYPE_REGION3: + index = (r2 >> 31) & 0x7ff; + break; + case _ASCE_TYPE_SEGMENT: + index = (r2 >> 20) & 0x7ff; + break; + } + for (i = 0; i < entries; i++) { + /* addresses are not wrapped in 24/31bit mode but table index is */ + raddr = table + ((index + i) & 0x7ff) * sizeof(entry); + entry = ldq_phys(cs->as, raddr); + if (!(entry & _REGION_ENTRY_INV)) { + /* we are allowed to not store if already invalid */ + entry |= _REGION_ENTRY_INV; + stq_phys(cs->as, raddr, entry); + } + } + } + + /* We simply flush the complete tlb, therefore we can ignore r3. */ + if (m4 & 1) { + tlb_flush(cs); + } else { + tlb_flush_all_cpus_synced(cs); + } +} + /* invalidate pte */ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, uint32_t m4) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 7efc10b..1be4c3a 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2407,6 +2407,21 @@ static ExitStatus op_ipm(DisasContext *s, DisasOps *o) } #ifndef CONFIG_USER_ONLY +static ExitStatus op_idte(DisasContext *s, DisasOps *o) +{ + TCGv_i32 m4; + + check_privileged(s); + if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { + m4 = tcg_const_i32(get_field(s->fields, m4)); + } else { + m4 = tcg_const_i32(0); + } + gen_helper_idte(cpu_env, o->in1, o->in2, m4); + tcg_temp_free_i32(m4); + return NO_EXIT; +} + static ExitStatus op_ipte(DisasContext *s, DisasOps *o) { TCGv_i32 m4;