From patchwork Fri Jul 7 02:20:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9829397 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9C90F602F0 for ; Fri, 7 Jul 2017 02:31:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 899B928449 for ; Fri, 7 Jul 2017 02:31:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7BC1F284B2; Fri, 7 Jul 2017 02:31:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EC7FB28449 for ; Fri, 7 Jul 2017 02:31:29 +0000 (UTC) Received: from localhost ([::1]:54142 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTJ3I-0008Rc-5E for patchwork-qemu-devel@patchwork.kernel.org; Thu, 06 Jul 2017 22:31:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34900) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTIwX-00038W-72 for qemu-devel@nongnu.org; Thu, 06 Jul 2017 22:24:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dTIwW-0000wq-4A for qemu-devel@nongnu.org; Thu, 06 Jul 2017 22:24:29 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:36582) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dTIwV-0000wV-VP for qemu-devel@nongnu.org; Thu, 06 Jul 2017 22:24:28 -0400 Received: by mail-qt0-x242.google.com with SMTP id v31so2716815qtb.3 for ; Thu, 06 Jul 2017 19:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=G4BQ3QrdP0w0sg22ycSTniDlHtjGPLKDzVbB8fTM2D8=; b=WssgfRueXELsdRG3XdlTYBzgkaKpJZ4oPKUxTWlKYQBK13m+eDnYtPvhTg6HMwnHwl 7LMI1ddVnph7jVk2e/nQjPAsTG+CAz4U4xAuiMVjr+LWUH4OVWQAUeWMH9qjCTxnbytu +2PsbpCY6MKp0+eCd/q41o2XbDJsdXX3zK3+PCs01kRWrq6JhH5qc3DCtuzVD016je9j 1hWjrQ6gPcsVITDabj/WlviNl4uZdTi1tiMLWURzP6yAYhLUcbGyzbw/igQPTl9pbVyi 4HrSfyg/6eHRwf2whFY4ZOhyPuyK1YLI9ifZPVfC99vj//5Fm0rVMga+lZ9bUhJLSUBr 8lmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=G4BQ3QrdP0w0sg22ycSTniDlHtjGPLKDzVbB8fTM2D8=; b=izhoeaIgj/2/4niT1ZIKfdHjpRZ3XAMtYhINEgauj8ILYbMoXKt/HPvmVfqM2nF9ly Bu3qm4LZJ9V3k+WR/R3nvtTB4zpF9lOxFRx6KtknE9DI19DKwNNPysGMI7mbF4sVHEpw 9xukksI3UQ3VVyegMZYWwE1LeZojg2PLj2yFJKYIeo60khwW/lz6/ZBnoUOeweDQKXxZ +emfw9ywMNRJpVFvPGuIPepj5eiqPt4fPfq9uIThDxjOkUTJXo14aLnpDkNxC8oQtlM4 0PolBmVll+/mEorsgbJNNuZHRLSP/eaW+G1viYo24oQU+22DEaUYo0zvFfpDeCsCPwPF SYQw== X-Gm-Message-State: AIVw113yHAQmrMyMmr7lA9MeNxc1sckq36hCJ0elC1B7+kBxG/uCF1KX UenmINMlmotCzmk4nZY= X-Received: by 10.200.35.21 with SMTP id a21mr34591714qta.56.1499394267304; Thu, 06 Jul 2017 19:24:27 -0700 (PDT) Received: from bigtime.twiddle.net.com (rrcs-66-91-136-156.west.biz.rr.com. [66.91.136.156]) by smtp.gmail.com with ESMTPSA id i85sm1407176qke.66.2017.07.06.19.24.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Jul 2017 19:24:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 6 Jul 2017 16:20:59 -1000 Message-Id: <20170707022111.21836-16-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170707022111.21836-1-rth@twiddle.net> References: <20170707022111.21836-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH v2 15/27] target/sh4: Merge DREG into fpr64 routines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno@clisp.org, laurent@vivier.eu, aurelien@aurel32.net, glaubitz@debian.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Also add a debugging assert that we did signal illegal opc for odd double-precision registers. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- target/sh4/translate.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b6c3ff9..616e615 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -346,11 +346,17 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { + /* We have already signaled illegal instruction for odd Dr. */ + tcg_debug_assert((reg & 1) == 0); + reg ^= ctx->fbank; tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); } static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { + /* We have already signaled illegal instruction for odd Dr. */ + tcg_debug_assert((reg & 1) == 0); + reg ^= ctx->fbank; tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); } @@ -369,8 +375,6 @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) #define FREG(x) cpu_fregs[(x) ^ ctx->fbank] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -/* Assumes lsb of (x) is always 0 */ -#define DREG(x) ((x) ^ ctx->fbank) #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -1100,8 +1104,8 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp0 = tcg_temp_new_i64(); fp1 = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp0, DREG(B11_8)); - gen_load_fpr64(ctx, fp1, DREG(B7_4)); + gen_load_fpr64(ctx, fp0, B11_8); + gen_load_fpr64(ctx, fp1, B7_4); switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1); @@ -1122,7 +1126,7 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1); return; } - gen_store_fpr64(ctx, fp0, DREG(B11_8)); + gen_store_fpr64(ctx, fp0, B11_8); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); } else { @@ -1714,7 +1718,7 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp = tcg_temp_new_i64(); gen_helper_float_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { @@ -1728,7 +1732,7 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } @@ -1750,9 +1754,9 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fsqrt_DT(fp, cpu_env, fp); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); @@ -1778,7 +1782,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv_i64 fp = tcg_temp_new_i64(); gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } return; @@ -1786,7 +1790,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED { TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); }