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[173.197.98.123]) by smtp.gmail.com with ESMTPSA id c63sm27368589pfk.79.2017.07.15.02.43.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 02:43:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 23:42:42 -1000 Message-Id: <20170715094243.28371-34-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v14 33/34] target/arm: Split out thumb_tr_translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, alex.bennee@linaro.org, vilanova@ac.upc.edu, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- target/arm/translate.c | 134 +++++++++++++++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 48 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ebe1c1a..d7c3c10 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11944,20 +11944,17 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, return true; } -static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +static bool arm_pre_translate_insn(DisasContext *dc) { - DisasContext *dc = container_of(dcbase, DisasContext, base); - CPUARMState *env = cpu->env_ptr; - #ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >= 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp = DISAS_NORETURN; - return; - } + /* Intercept jump to the magic kernel page. */ + if (dc->pc >= 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp = DISAS_NORETURN; + return true; + } #endif if (dc->ss_active && !dc->pstate_ss) { @@ -11975,54 +11972,82 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->base.is_jmp = DISAS_NORETURN; - return; + return true; } - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond = (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask == 0) { - dc->condexec_cond = 0; - } - } - } else { - unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc += 4; - disas_arm_insn(dc, insn); + return false; +} + +static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +{ + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp == DISAS_NEXT + && (dc->pc >= dc->next_page_start + || (dc->pc >= dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp = DISAS_TOO_MANY; } if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp = 0; } + dc->base.pc_next = dc->pc; + translator_loop_temp_check(&dc->base); +} - if (dc->base.is_jmp == DISAS_NEXT) { - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - if (dc->pc >= dc->next_page_start || - (dc->pc >= dc->next_page_start - 3 && - insn_crosses_page(env, dc))) { - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - dc->base.is_jmp = DISAS_TOO_MANY; +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + unsigned int insn; + + if (arm_pre_translate_insn(dc)) { + return; + } + + insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc += 4; + disas_arm_insn(dc, insn); + + arm_post_translate_insn(env, dc); +} + +static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + + if (arm_pre_translate_insn(dc)) { + return; + } + + disas_thumb_insn(env, dc); + + /* Advance the Thumb condexec condition. */ + if (dc->condexec_mask) { + dc->condexec_cond = ((dc->condexec_cond & 0xe) | + ((dc->condexec_mask >> 4) & 1)); + dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask == 0) { + dc->condexec_cond = 0; } } - dc->base.pc_next = dc->pc; - translator_loop_temp_check(&dc->base); + arm_post_translate_insn(env, dc); } static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -12161,12 +12186,25 @@ static const TranslatorOps arm_translator_ops = { .disas_log = arm_tr_disas_log, }; +static const TranslatorOps thumb_translator_ops = { + .init_disas_context = arm_tr_init_disas_context, + .tb_start = arm_tr_tb_start, + .insn_start = arm_tr_insn_start, + .breakpoint_check = arm_tr_breakpoint_check, + .translate_insn = thumb_tr_translate_insn, + .tb_stop = arm_tr_tb_stop, + .disas_log = arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc; const TranslatorOps *ops = &arm_translator_ops; + if (ARM_TBFLAG_THUMB(tb->flags)) { + ops = &thumb_translator_ops; + } #ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { ops = &aarch64_translator_ops;