From patchwork Tue Jul 18 14:24:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cornelia Huck X-Patchwork-Id: 9848645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B0637600CC for ; Tue, 18 Jul 2017 14:44:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F9C32624A for ; Tue, 18 Jul 2017 14:44:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9435028549; Tue, 18 Jul 2017 14:44:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2C90F2624A for ; Tue, 18 Jul 2017 14:44:46 +0000 (UTC) Received: from localhost ([::1]:56933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXTjy-0008HE-9Y for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Jul 2017 10:44:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58185) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXTQy-0006ne-9v for qemu-devel@nongnu.org; Tue, 18 Jul 2017 10:25:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXTQx-0004k3-8p for qemu-devel@nongnu.org; Tue, 18 Jul 2017 10:25:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54944) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dXTQw-0004jG-Vh for qemu-devel@nongnu.org; Tue, 18 Jul 2017 10:25:07 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E34B9C04D293; Tue, 18 Jul 2017 14:25:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com E34B9C04D293 Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=cohuck@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com E34B9C04D293 Received: from localhost (dhcp-192-215.str.redhat.com [10.33.192.215]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 85C217F467; Tue, 18 Jul 2017 14:25:05 +0000 (UTC) From: Cornelia Huck To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 16:24:49 +0200 Message-Id: <20170718142455.32676-4-cohuck@redhat.com> In-Reply-To: <20170718142455.32676-1-cohuck@redhat.com> References: <20170718142455.32676-1-cohuck@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 18 Jul 2017 14:25:06 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH RFC v2 3/9] s390x: chsc nt2 events are pci-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, zyimin@linux.vnet.ibm.com, Cornelia Huck , pmorel@linux.vnet.ibm.com, agraf@suse.de, borntraeger@de.ibm.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The nt2 event class is pci-only - don't look for events if pci is not in the active cpu model. Signed-off-by: Cornelia Huck --- hw/s390x/s390-pci-bus.c | 4 ++-- hw/s390x/s390-pci-bus.h | 4 ++-- hw/s390x/s390-pci-stub.c | 4 ++-- target/s390x/ioinst.c | 16 ++++++++++++++++ 4 files changed, 22 insertions(+), 6 deletions(-) diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 61cfd2138f..c57f6ebae0 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -47,7 +47,7 @@ S390pciState *s390_get_phb(void) return phb; } -int chsc_sei_nt2_get_event(void *res) +int pci_chsc_sei_nt2_get_event(void *res) { ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res; PciCcdfAvail *accdf; @@ -87,7 +87,7 @@ int chsc_sei_nt2_get_event(void *res) return rc; } -int chsc_sei_nt2_have_event(void) +int pci_chsc_sei_nt2_have_event(void) { S390pciState *s = s390_get_phb(); diff --git a/hw/s390x/s390-pci-bus.h b/hw/s390x/s390-pci-bus.h index 67af2c12ff..5df6292509 100644 --- a/hw/s390x/s390-pci-bus.h +++ b/hw/s390x/s390-pci-bus.h @@ -319,8 +319,8 @@ typedef struct S390pciState { } S390pciState; S390pciState *s390_get_phb(void); -int chsc_sei_nt2_get_event(void *res); -int chsc_sei_nt2_have_event(void); +int pci_chsc_sei_nt2_get_event(void *res); +int pci_chsc_sei_nt2_have_event(void); void s390_pci_sclp_configure(SCCB *sccb); void s390_pci_sclp_deconfigure(SCCB *sccb); void s390_pci_iommu_enable(S390PCIIOMMU *iommu); diff --git a/hw/s390x/s390-pci-stub.c b/hw/s390x/s390-pci-stub.c index 2e7e42a2af..cc7278a865 100644 --- a/hw/s390x/s390-pci-stub.c +++ b/hw/s390x/s390-pci-stub.c @@ -7,12 +7,12 @@ #include "s390-pci-bus.h" /* target/s390x/ioinst.c */ -int chsc_sei_nt2_get_event(void *res) +int pci_chsc_sei_nt2_get_event(void *res) { return 1; } -int chsc_sei_nt2_have_event(void) +int pci_chsc_sei_nt2_have_event(void) { return 0; } diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c index d5e6b8066b..a9e5b13292 100644 --- a/target/s390x/ioinst.c +++ b/target/s390x/ioinst.c @@ -599,6 +599,22 @@ static int chsc_sei_nt0_have_event(void) return 0; } +static int chsc_sei_nt2_get_event(void *res) +{ + if (s390_has_feat(S390_FEAT_ZPCI)) { + return pci_chsc_sei_nt2_get_event(res); + } + return 1; +} + +static int chsc_sei_nt2_have_event(void) +{ + if (s390_has_feat(S390_FEAT_ZPCI)) { + return pci_chsc_sei_nt2_have_event(); + } + return 0; +} + #define CHSC_SEI_NT0 (1ULL << 63) #define CHSC_SEI_NT2 (1ULL << 61) static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)