From patchwork Tue Jul 18 21:50:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 9849853 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 73F27602C8 for ; Tue, 18 Jul 2017 22:02:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C38E28607 for ; Tue, 18 Jul 2017 22:02:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5153A28613; Tue, 18 Jul 2017 22:02:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CFB6428607 for ; Tue, 18 Jul 2017 22:02:17 +0000 (UTC) Received: from localhost ([::1]:58789 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaZM-0006PT-Lg for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Jul 2017 18:02:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48598) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaPl-0005jP-6r for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXaPk-0003zc-8a for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:21 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:48432) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dXaOY-0003Uw-3K for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:20 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dXaOU-0000KI-F1; Tue, 18 Jul 2017 23:51:02 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dXaOQ-00013M-6a; Tue, 18 Jul 2017 23:50:58 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 23:50:40 +0200 Message-Id: <20170718215050.3812-22-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170718215050.3812-1-aurelien@aurel32.net> References: <20170718215050.3812-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 21/31] target/sh4: Simplify 64-bit fp reg-reg move X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Henderson We do not need to form full 64-bit quantities in order to perform the move. This reduces code expansion on 64-bit hosts. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson Message-Id: <20170718200255.31647-18-rth@twiddle.net> Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 7dfe23d1f4..792a46804b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -981,10 +981,10 @@ static void _decode_opc(DisasContext * ctx) case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, XHACK(B7_4)); - gen_store_fpr64(ctx, fp, XHACK(B11_8)); - tcg_temp_free_i64(fp); + int xsrc = XHACK(B7_4); + int xdst = XHACK(B11_8); + tcg_gen_mov_i32(FREG(xdst), FREG(xsrc)); + tcg_gen_mov_i32(FREG(xdst + 1), FREG(xsrc + 1)); } else { tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4)); }