From patchwork Tue Jul 18 21:50:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 9849741 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5CA2460392 for ; Tue, 18 Jul 2017 21:53:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 44ED3285FD for ; Tue, 18 Jul 2017 21:53:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3A13828600; Tue, 18 Jul 2017 21:53:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ADE49285FD for ; Tue, 18 Jul 2017 21:53:36 +0000 (UTC) Received: from localhost ([::1]:58748 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaQx-0005nk-Ue for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Jul 2017 17:53:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXaPl-0005jc-E3 for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXaPk-00040M-Fp for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:21 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:48510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dXaOY-0003VG-3s for qemu-devel@nongnu.org; Tue, 18 Jul 2017 17:52:20 -0400 Received: from [2001:bc8:30d7:120:9bb5:8936:7e6a:9e36] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1dXaOT-0000K8-6a; Tue, 18 Jul 2017 23:51:01 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.89) (envelope-from ) id 1dXaOO-00011e-Rz; Tue, 18 Jul 2017 23:50:56 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 23:50:25 +0200 Message-Id: <20170718215050.3812-7-aurelien@aurel32.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170718215050.3812-1-aurelien@aurel32.net> References: <20170718215050.3812-1-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:bc8:30d7:100::1 Subject: [Qemu-devel] [PULL 06/31] target/sh4: Consolidate end-of-TB tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Henderson We can fold 3 different tests within the decode loop into a more accurate computation of max_insns to start. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson Message-Id: <20170718200255.31647-3-rth@twiddle.net> Signed-off-by: Aurelien Jarno --- target/sh4/translate.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 4c3512f62f..310c52ad2a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1830,17 +1830,28 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) ctx.features = env->features; ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA); - num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; + max_insns = MIN(max_insns, TCG_MAX_INSNS); + + /* Since the ISA is fixed-width, we can bound by the number + of instructions remaining on the page. */ + num_insns = -(ctx.pc | TARGET_PAGE_MASK) / 2; + max_insns = MIN(max_insns, num_insns); + + /* Single stepping means just that. */ + if (ctx.singlestep_enabled || singlestep) { + max_insns = 1; } gen_tb_start(tb); - while (ctx.bstate == BS_NONE && !tcg_op_buf_full()) { + num_insns = 0; + + while (ctx.bstate == BS_NONE + && num_insns < max_insns + && !tcg_op_buf_full()) { tcg_gen_insn_start(ctx.pc, ctx.envflags); num_insns++; @@ -1864,18 +1875,10 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) ctx.opcode = cpu_lduw_code(env, ctx.pc); decode_opc(&ctx); ctx.pc += 2; - if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) - break; - if (cs->singlestep_enabled) { - break; - } - if (num_insns >= max_insns) - break; - if (singlestep) - break; } - if (tb->cflags & CF_LAST_IO) + if (tb->cflags & CF_LAST_IO) { gen_io_end(); + } if (cs->singlestep_enabled) { gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env);