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X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PULL v2 10/14] target/sparc: optimize various functions using extract op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Philippe Mathieu-Daudé Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index aa6734d54e..67a83b77cc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -380,29 +380,25 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); - tcg_gen_andi_tl(reg, reg, 0x1); + tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1); } static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); - tcg_gen_andi_tl(reg, reg, 0x1); + tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1); } static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); - tcg_gen_andi_tl(reg, reg, 0x1); + tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1); } static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); - tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); - tcg_gen_andi_tl(reg, reg, 0x1); + tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1); } static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) @@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) // env->y = (b2 << 31) | (env->y >> 1); tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); tcg_gen_shli_tl(r_temp, r_temp, 31); - tcg_gen_shri_tl(t0, cpu_y, 1); - tcg_gen_andi_tl(t0, t0, 0x7fffffff); + tcg_gen_extract_tl(t0, cpu_y, 1, 31); tcg_gen_or_tl(t0, t0, r_temp); tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);