From patchwork Mon Jul 24 20:27:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9860529 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6EBA160349 for ; Mon, 24 Jul 2017 20:53:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61868284F4 for ; Mon, 24 Jul 2017 20:53:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 56695285CA; Mon, 24 Jul 2017 20:53:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9058A284F4 for ; Mon, 24 Jul 2017 20:53:21 +0000 (UTC) Received: from localhost ([::1]:56944 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkLw-0006Bh-PA for patchwork-qemu-devel@patchwork.kernel.org; Mon, 24 Jul 2017 16:53:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48032) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjy3-0003aL-Bb for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxz-0001Tc-1Z for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:39 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:33050) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxy-0001Si-QE for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:34 -0400 Received: by mail-qt0-x243.google.com with SMTP id n42so3407926qtn.0 for ; Mon, 24 Jul 2017 13:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RopMAEV/SJSgs03eysJLbPN+OAhxnY4as4CqzVaGesE=; b=BemboevYaWFPMPFV2XMZv0loTRgYwEqgr21Lnon62V2O/ycsnEJa0aeSf1VWCy8fcl qEJ0Ok6g7YEmqMe4zTKoV0VMp/1hHqusIFkYvQ7F8r2qn96mWCWS2FoH2qjMcZr4JH4R dRpAFt89aD3l8117E3pkvRjAAR6rcX/3eYHnQxDdnydOKImvWsLIl2fhxwDirZSlAjfV 1ecLSkPJ9HytBrqymTYcxfVPqo7itEBepkpFRSUPQ0Le58q7xffcbX/o1MK9VZoBK+Gm lta4Xh5enkKojzF80qDANb2c0GflF5ZO71Y0PwATrIdMU792cxPK1zYunqiZjH/u3JQs k3cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RopMAEV/SJSgs03eysJLbPN+OAhxnY4as4CqzVaGesE=; b=VGwE4v6LdiwvswZccrVA9T/AK8pWiNxjHymsY2qi0S6RvasWf8Ule1+mYykO4XbfU6 xd/4fBNkYB/BrtYVxBHXV71fpzMfZcZyG4CTG5sKR/FA8t6/fCKTNYPktkXJQdGq2U4/ vmPIPBbBo7hSpmNVESy+pJ/MtL0oK1sryBczXIhuTRV923tFnWAAjJdP0V6eZNo9Fl+H rV8ScbTdssClq3tKdz1umMJMkyGf2vnVBOT1UiHY4x2CLsgz3h2VI1GLiKtfbNc1/bLr thimK3InuJUTQ1oANPxXmuZlng2ZT3Mqs0U9GgYJe6MwfX79sUz3t1Zo5cYn/K13A79R el7A== X-Gm-Message-State: AIVw111Z7FLSGXJCL1r9tU4kzTfw7Z8FgkEWOccpVv7HC5SWopBnDMRb 0USzLfFOHP19gfmA8uI= X-Received: by 10.200.34.173 with SMTP id f42mr8994996qta.150.1500928113861; Mon, 24 Jul 2017 13:28:33 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:18 -0700 Message-Id: <20170724202728.25960-23-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH v15 22/32] target/arm: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/translate.c | 165 +++++++++++++++++++++++++++---------------------- 2 files changed, 91 insertions(+), 75 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index a804ff65ac..e8dcec51ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,6 +9,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; + target_ulong next_page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 30db22fa79..0b4cb1e463 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11850,6 +11850,8 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, dc->is_ldex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ + dc->next_page_start = + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); @@ -11943,14 +11945,93 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, return true; } +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUARMState *env = cpu->env_ptr; + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >= 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp = DISAS_NORETURN; + return; + } +#endif + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns == 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp = DISAS_NORETURN; + return; + } + + if (dc->thumb) { + disas_thumb_insn(env, dc); + if (dc->condexec_mask) { + dc->condexec_cond = (dc->condexec_cond & 0xe) + | ((dc->condexec_mask >> 4) & 1); + dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask == 0) { + dc->condexec_cond = 0; + } + } + } else { + unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc += 4; + disas_arm_insn(dc, insn); + } + + if (dc->condjmp && !dc->base.is_jmp) { + gen_set_label(dc->condlabel); + dc->condjmp = 0; + } + + if (dc->base.is_jmp == DISAS_NEXT) { + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. */ + + if (is_singlestepping(dc)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((dc->pc >= dc->next_page_start) || + ((dc->pc >= dc->next_page_start - 3) && + insn_crosses_page(env, dc))) { + /* We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + dc->base.is_jmp = DISAS_TOO_MANY; + } + } + + dc->base.pc_next = dc->pc; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUARMState *env = cs->env_ptr; DisasContext dc1, *dc = &dc1; - target_ulong next_page_start; int max_insns; - bool end_of_page; /* generate intermediate code */ @@ -11969,7 +12050,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->base.num_insns = 0; dc->base.singlestep_enabled = cs->singlestep_enabled; - next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; @@ -12006,83 +12086,18 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_io_start(); } -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >= 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp = DISAS_NORETURN; - break; - } -#endif - - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debugged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp = DISAS_NORETURN; - break; - } - - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond = (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask == 0) { - dc->condexec_cond = 0; - } - } - } else { - unsigned int insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc += 4; - disas_arm_insn(dc, insn); - } - - if (dc->condjmp && !dc->base.is_jmp) { - gen_set_label(dc->condlabel); - dc->condjmp = 0; - } + arm_tr_translate_insn(&dc->base, cs); if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - end_of_page = (dc->pc >= next_page_start) || - ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc)); - - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !is_singlestepping(dc) && - !singlestep && - !end_of_page && - dc->base.num_insns < max_insns); + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >= max_insns)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) {