From patchwork Mon Jul 24 20:27:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9860411 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4F39A6038F for ; Mon, 24 Jul 2017 20:44:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 424C7285AE for ; Mon, 24 Jul 2017 20:44:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 37426285C0; Mon, 24 Jul 2017 20:44:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 28BF3285C3 for ; Mon, 24 Jul 2017 20:44:47 +0000 (UTC) Received: from localhost ([::1]:56884 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkDE-0006pU-Ar for patchwork-qemu-devel@patchwork.kernel.org; Mon, 24 Jul 2017 16:44:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjy3-0003aS-FC for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjy1-0001ZG-Qz for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:39 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:33458) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjy1-0001Yb-LS for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:37 -0400 Received: by mail-qk0-x244.google.com with SMTP id d145so8411191qkc.0 for ; Mon, 24 Jul 2017 13:28:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HFc9+x9yMJuoLkssT25OglTsJe7tkSG6TnkXKcH7kYY=; b=ueH+jVomCUx/BcuLoAP5Q9ZfWv1VMBYIFkgNqRVOfLHLTJFAVw1mMgw1gGW9wB2yef jwqqJNrNBcC+3T6FcuVHe/3soIy5FHl+JrQBy64ovt3IwirsD/W4HbY0lHeXHTO2rl7T y3xM/q27orrWUXPkPRGLx2IVAT7GQ4P3snWaFOmTz7qlJsxktm4toF6jguHSNSbVtcK3 IkwXcNOIezZVM4vN4Ff0Mzomc+S/yyXoNTWJCMAx7ltBDMht8662oN81Njn/XHi2nsjA YPrAjsHD3iWXftMxlzS474vMJ5Jm3SP7J0yZWRhGTFt64fRlne8IaLy4w0l4wrwfxqjd RDyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HFc9+x9yMJuoLkssT25OglTsJe7tkSG6TnkXKcH7kYY=; b=p0Hxw3hvM2z/SPqsbUku3zdgdRKS+u+gSgDA6McUxitolv459Jzq07zZ954Sh4mZhE MTodaYTpuDRAXs6xrjMVOrpdfWOIiZErDP+aDUbsINc/Cs3niVk+/3lVhBm/enL1RpU4 nIS9JIAPwLNFGkJ/1XY3H2odlzHBp6ryzyqYvkqDBwe+EM57jCJdtV67dRTlYm4g2TsI i4VlZiwl9b7iJSKsVPBeMTGTu6JqlzMLpv5PJi3anQiHEVWQ/DOoQTxu7oZCqGGI7YjR 9+QDNs2txnPuMz1wTx4uc7SvN/jHotLkgrej4nqz+5AbTTc1FMwFUJBpLm5gvEtbbc6G HqoQ== X-Gm-Message-State: AIVw110+yDEBgoilDMdlvu4LmvfKbEmEdcGhn6fGsFQPD5ymANp1/A+Y C5lt5/LSodZral5zaIA= X-Received: by 10.55.97.13 with SMTP id v13mr22371824qkb.107.1500928116797; Mon, 24 Jul 2017 13:28:36 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:20 -0700 Message-Id: <20170724202728.25960-25-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 24/32] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Reviewed-by: Emilio G. Cota Signed-off-by: Lluís Vilanova Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 161 ++++++++++++++++++++++++++----------------------- 1 file changed, 84 insertions(+), 77 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0b4cb1e463..bacc0303e5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12027,85 +12027,13 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->base.pc_next = dc->pc; } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc = &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/etc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; - - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >= max_insns)) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); + DisasContext *dc = container_of(dcbase, DisasContext, base); - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. */ + cpu_abort(cpu, "IO on conditional branch instruction"); } /* At this stage dc->condjmp will only be set when the skipped @@ -12211,6 +12139,85 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc1, *dc = &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/etc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; + + max_insns = tb->cflags & CF_COUNT_MASK; + if (max_insns == 0) { + max_insns = CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns = TCG_MAX_INSNS; + } + max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns); + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); + + do { + dc->base.num_insns++; + arm_tr_insn_start(&dc->base, cs); + + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc == dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } + } + + if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + gen_io_start(); + } + + arm_tr_translate_insn(&dc->base, cs); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >= max_insns)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + arm_tr_tb_stop(&dc->base, cs); gen_tb_end(tb, dc->base.num_insns);