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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:19 -0700 Message-Id: <20170804054426.10590-17-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH for-2.11 16/23] tcg/arm: Tighten tlb indexing offset test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP We are not going to use ldrd for loading the comparator for 32-bit guests, so don't limit cmp_off to 8 bits then. This eliminates one insn in the tlb load for some guests. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 66c369c239..6c12b169ce 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1202,7 +1202,9 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, } /* We checked that the offset is contained within 16 bits above. */ - if (add_off > 0xfff || (use_armv6_instructions && cmp_off > 0xff)) { + if (add_off > 0xfff + || (use_armv6_instructions && TARGET_LONG_BITS == 64 + && cmp_off > 0xff)) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, (24 << 7) | (cmp_off >> 8)); base = TCG_REG_R2;