From patchwork Mon Aug 28 03:53:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pranith Kumar X-Patchwork-Id: 9924117 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8F31E60329 for ; Mon, 28 Aug 2017 03:54:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7CA3E1FF2C for ; Mon, 28 Aug 2017 03:54:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7124B285DA; Mon, 28 Aug 2017 03:54:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DEBDE1FF2C for ; Mon, 28 Aug 2017 03:54:31 +0000 (UTC) Received: from localhost ([::1]:36793 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmB8A-0003kj-4X for patchwork-qemu-devel@patchwork.kernel.org; Sun, 27 Aug 2017 23:54:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55762) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmB7I-0003jE-0C for qemu-devel@nongnu.org; Sun, 27 Aug 2017 23:53:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmB7G-00042k-T6 for qemu-devel@nongnu.org; Sun, 27 Aug 2017 23:53:36 -0400 Received: from mail-yw0-x242.google.com ([2607:f8b0:4002:c05::242]:34179) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmB7D-0003xh-AP; Sun, 27 Aug 2017 23:53:31 -0400 Received: by mail-yw0-x242.google.com with SMTP id h127so2734835ywf.1; Sun, 27 Aug 2017 20:53:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NKneIklgXd1r8SxdWzvYWVqIn/IWKcCDCp5OlI41SWU=; b=HwAHAtEtDIZQHZHlwbzcsSIOxxnA54XSXqkewVNX28Kv5f15J1hh8ZA6DfQyqKIqCd Qe54VTIarZeQF2XZWprouccFPkKq00SiWEXxdbuUxokG/3YusYDSiAs/GrR5kqOGhW3b GeRbBXn6KmGnBWix0BuZmyS80o8kYvN68f45H5Aqgl8W6Yw7EBRTa3CJmrS1f4Lywr0E UCSaZujo5H8/xUcAPEQ3Y6Af/nr/4wUXHB2ligsC//z060azMW5Pl4HrTHdxd45AonHx nPQ9HNZxDSqPE3EUmO6wrEVNsL7JPZN8+hASITWHSDYXt5HY6n9rZxMcmTuX1NamxWnW BhKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NKneIklgXd1r8SxdWzvYWVqIn/IWKcCDCp5OlI41SWU=; b=H55lNEfAy/sN72TQ8/HopOof0JUZS8dK/Y/qzWPqiU/TuBksAvTr9e1mpfYHNZWmLt d9f807zjFIzJuTWurlJAP6ZE2sqca0qAgNfcIiZxlKz3qkEwUxRjfrli9l+7o57dMvv6 fFSoxx8inSnOCs+2LkB4nLsRfaPbUNFUrpHbJecDQ3APcfCPasRhl7xWPLDWLSq92Oy4 1tkqUuxgWbI6V9KVua6eV3KQSpYxIZ9KKxHKOVZaoZa1OUrIopjVxmGqi4V9vqjWsetX fnp7KSlJReM7+VMGiSs65UjCdBCasce4Mpm7CutMOeEDiBBXJ2EnH0Gvl+c05TMy2mTi oYHQ== X-Gm-Message-State: AHYfb5g9wXiNd4ZiHsEATG6y1sKYrtCoC4N4mIxisqsHGstl7Cd9u0Uv mfy1hI1VcWqWlQ== X-Received: by 10.37.14.212 with SMTP id 203mr4858559ybo.164.1503892410621; Sun, 27 Aug 2017 20:53:30 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id i64sm4820865ywi.64.2017.08.27.20.53.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 27 Aug 2017 20:53:30 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org, Claudio Fontana , Richard Henderson , Andrzej Zaborowski , Aurelien Jarno , qemu-arm@nongnu.org (open list:AArch64 target), qemu-devel@nongnu.org (open list:All patches CC here) Date: Sun, 27 Aug 2017 23:53:26 -0400 Message-Id: <20170828035327.17146-3-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170828035327.17146-1-bobby.prani@gmail.com> References: <20170828035327.17146-1-bobby.prani@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::242 Subject: [Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering semantics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Currently, we cannot use mttcg for running strong memory model guests on weak memory model hosts due to missing ordering semantics. We implicitly generate fence instructions for stronger guests if an ordering mismatch is detected. We generate fences only for the orders for which fence instructions are necessary, for example a fence is not necessary between a store and a subsequent load on x86 since its absence in the guest binary tells that ordering need not be ensured. Also note that if we find multiple subsequent fence instructions in the generated IR, we combine them in the TCG optimization pass. This patch allows us to boot an x86 guest on ARM64 hosts using mttcg. Signed-off-by: Pranith Kumar --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/tcg-op.c | 17 +++++++++++++++++ tcg/tcg-op.h | 1 + 6 files changed, 26 insertions(+) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..b41a248bee 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *)start, (char *)stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5ef1086710..a38be15a39 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -134,4 +134,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *) start, (char *) stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..e9558d15bc 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -206,4 +206,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) cacheflush ((void *)start, stop-start, ICACHE); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5f4a40a5b4..5a092b038a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -125,4 +125,6 @@ extern bool have_isa_3_00; void flush_icache_range(uintptr_t start, uintptr_t stop); +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673ef49..085fe66fb2 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,6 +28,7 @@ #include "exec/exec-all.h" #include "tcg.h" #include "tcg-op.h" +#include "tcg-mo.h" #include "trace-tcg.h" #include "trace/mem.h" @@ -2662,8 +2663,21 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, #endif } +void tcg_gen_req_mo(TCGBar type) +{ +#if defined(TCG_GUEST_DEFAULT_MO) && defined(TCG_TARGET_DEFAULT_MO) + TCGBar order_mismatch = type & (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO); + if (order_mismatch) { + tcg_gen_mb(order_mismatch | TCG_BAR_SC); + } +#else + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); +#endif +} + void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST); memop = tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 0)); @@ -2672,6 +2686,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); memop = tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 1)); @@ -2680,6 +2695,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_LD_ST); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2698,6 +2714,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return; diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f243..6ad2c6d60e 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -262,6 +262,7 @@ static inline void tcg_gen_br(TCGLabel *l) } void tcg_gen_mb(TCGBar); +void tcg_gen_req_mo(TCGBar type); /* Helper calls. */