From patchwork Fri Oct 20 11:53:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cornelia Huck X-Patchwork-Id: 10020005 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6FB0860234 for ; Fri, 20 Oct 2017 12:02:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5E55B28524 for ; Fri, 20 Oct 2017 12:02:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 523BF28B24; Fri, 20 Oct 2017 12:02:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 84AFE28524 for ; Fri, 20 Oct 2017 12:02:28 +0000 (UTC) Received: from localhost ([::1]:53321 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e5W0R-0008Md-LT for patchwork-qemu-devel@patchwork.kernel.org; Fri, 20 Oct 2017 08:02:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e5Vt2-000297-9E for qemu-devel@nongnu.org; Fri, 20 Oct 2017 07:54:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e5Vt1-0002tE-8m for qemu-devel@nongnu.org; Fri, 20 Oct 2017 07:54:48 -0400 Received: from mx1.redhat.com ([209.132.183.28]:29060) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e5Vt0-0002rp-W4; Fri, 20 Oct 2017 07:54:47 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id DB6A833A178; Fri, 20 Oct 2017 11:54:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com DB6A833A178 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=cohuck@redhat.com Received: from localhost (dhcp-192-222.str.redhat.com [10.33.192.222]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 848C4600C0; Fri, 20 Oct 2017 11:54:45 +0000 (UTC) From: Cornelia Huck To: peter.maydell@linaro.org Date: Fri, 20 Oct 2017 13:53:38 +0200 Message-Id: <20171020115418.2050-7-cohuck@redhat.com> In-Reply-To: <20171020115418.2050-1-cohuck@redhat.com> References: <20171020115418.2050-1-cohuck@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Fri, 20 Oct 2017 11:54:46 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 06/46] s390x/tcg: rework checking for deliverable interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, david@redhat.com, Cornelia Huck , agraf@suse.de, qemu-devel@nongnu.org, borntraeger@de.ibm.com, qemu-s390x@nongnu.org, rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: David Hildenbrand Currently, enabling/disabling of interrupts is not really supported. Let's improve interrupt handling code by explicitly checking for deliverable interrupts only. This is the first step. Checking for external interrupt subclasses will be done next. Signed-off-by: David Hildenbrand Message-Id: <20170928203708.9376-5-david@redhat.com> Reviewed-by: Richard Henderson Signed-off-by: Cornelia Huck --- target/s390x/cpu.c | 8 +++++--- target/s390x/excp_helper.c | 21 +++++++-------------- target/s390x/internal.h | 4 ++++ target/s390x/interrupt.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 17 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 77d55c9e1e..b0517475fa 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -56,10 +56,12 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) static bool s390_cpu_has_work(CPUState *cs) { S390CPU *cpu = S390_CPU(cs); - CPUS390XState *env = &cpu->env; - return (cs->interrupt_request & CPU_INTERRUPT_HARD) && - (env->psw.mask & PSW_MASK_EXT); + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + return s390_cpu_has_int(cpu); } #if !defined(CONFIG_USER_ONLY) diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 44e9b2c6a6..050d5a61f1 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -435,24 +435,16 @@ void s390_cpu_do_interrupt(CPUState *cs) s390_cpu_set_state(CPU_STATE_OPERATING, cpu); /* handle machine checks */ - if ((env->psw.mask & PSW_MASK_MCHECK) && - (cs->exception_index == -1)) { - if (env->pending_int & INTERRUPT_MCHK) { - cs->exception_index = EXCP_MCHK; - } + if (cs->exception_index == -1 && s390_cpu_has_mcck_int(cpu)) { + cs->exception_index = EXCP_MCHK; } /* handle external interrupts */ - if ((env->psw.mask & PSW_MASK_EXT) && - cs->exception_index == -1 && - (env->pending_int & INTERRUPT_EXT)) { + if (cs->exception_index == -1 && s390_cpu_has_ext_int(cpu)) { cs->exception_index = EXCP_EXT; } /* handle I/O interrupts */ - if ((env->psw.mask & PSW_MASK_IO) && - (cs->exception_index == -1)) { - if (env->pending_int & INTERRUPT_IO) { - cs->exception_index = EXCP_IO; - } + if (cs->exception_index == -1 && s390_cpu_has_io_int(cpu)) { + cs->exception_index = EXCP_IO; } switch (cs->exception_index) { @@ -474,6 +466,7 @@ void s390_cpu_do_interrupt(CPUState *cs) } cs->exception_index = -1; + /* we might still have pending interrupts, but not deliverable */ if (!env->pending_int) { cs->interrupt_request &= ~CPU_INTERRUPT_HARD; } @@ -490,7 +483,7 @@ bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request) the parent EXECUTE insn. */ return false; } - if (env->psw.mask & PSW_MASK_EXT) { + if (s390_cpu_has_int(cpu)) { s390_cpu_do_interrupt(cs); return true; } diff --git a/target/s390x/internal.h b/target/s390x/internal.h index f67c2a1785..e41fb2e38e 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -364,6 +364,10 @@ void cpu_inject_clock_comparator(S390CPU *cpu); void cpu_inject_cpu_timer(S390CPU *cpu); void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr); int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr); +bool s390_cpu_has_io_int(S390CPU *cpu); +bool s390_cpu_has_ext_int(S390CPU *cpu); +bool s390_cpu_has_mcck_int(S390CPU *cpu); +bool s390_cpu_has_int(S390CPU *cpu); /* ioinst.c */ diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index bb7cc7f87f..0cb65a8c46 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -190,4 +190,50 @@ void s390_crw_mchk(void) } } +bool s390_cpu_has_mcck_int(S390CPU *cpu) +{ + CPUS390XState *env = &cpu->env; + + if (!(env->psw.mask & PSW_MASK_MCHECK)) { + return false; + } + + return env->pending_int & INTERRUPT_MCHK; +} + +bool s390_cpu_has_ext_int(S390CPU *cpu) +{ + CPUS390XState *env = &cpu->env; + + if (!(env->psw.mask & PSW_MASK_EXT)) { + return false; + } + + return env->pending_int & INTERRUPT_EXT; +} + +bool s390_cpu_has_io_int(S390CPU *cpu) +{ + CPUS390XState *env = &cpu->env; + + if (!(env->psw.mask & PSW_MASK_IO)) { + return false; + } + + return env->pending_int & INTERRUPT_IO; +} #endif + +bool s390_cpu_has_int(S390CPU *cpu) +{ +#ifndef CONFIG_USER_ONLY + if (!tcg_enabled()) { + return false; + } + return s390_cpu_has_mcck_int(cpu) || + s390_cpu_has_ext_int(cpu) || + s390_cpu_has_io_int(cpu); +#else + return false; +#endif +}