From patchwork Fri Oct 20 23:19:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10021181 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9063F603B5 for ; Fri, 20 Oct 2017 23:41:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 83A4628F07 for ; Fri, 20 Oct 2017 23:41:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7899928F09; Fri, 20 Oct 2017 23:41:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E279428F08 for ; Fri, 20 Oct 2017 23:41:49 +0000 (UTC) Received: from localhost ([::1]:56063 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e5gvF-0007dq-4F for patchwork-qemu-devel@patchwork.kernel.org; Fri, 20 Oct 2017 19:41:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44433) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e5gb2-00064y-Jm for qemu-devel@nongnu.org; Fri, 20 Oct 2017 19:21:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e5gb1-0007gn-9i for qemu-devel@nongnu.org; Fri, 20 Oct 2017 19:20:56 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:47095) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e5gb1-0007gZ-1f for qemu-devel@nongnu.org; Fri, 20 Oct 2017 19:20:55 -0400 Received: by mail-pf0-x242.google.com with SMTP id p87so13073631pfj.3 for ; Fri, 20 Oct 2017 16:20:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pHBBmAhFgGlIKUJfyIBoSXcM/90l/Bevuy8gOK+6lXw=; b=ePRXI0bLiXbwxDKVmlHjBS/e6ToaPJOwjXEA+syHrlovZBeVu5XPxErNl/cpAyxQOQ k/DKou5mlAtDmDvxmuqZ3X+bqikNSHCBp7b8L+oJSKQVy1J0FmRmraxWHdEAAvGsmiax kd6alroMGegtgHXipaoxyphsiXYscJUIwljZc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pHBBmAhFgGlIKUJfyIBoSXcM/90l/Bevuy8gOK+6lXw=; b=tJQha65+k4+ePXnTGqf52/IMkSmE+UFZJFt8l5ZSTxleLwE1XiskwPqlQWXBuiH/Uq 81Ej+VcraoiTe9hd0EAtcyR0HffZ8mIGx/3IK6kjdM3ZEQq9+C9HlVFh3P67fZ7MxAUY aDmwEAcWrfxMRTm9HgzexSw7XW4zW5EkWfHahAxNpkHbwTlVsFDf4/xcICHvBbiHh4r1 as2ARHR/9TJ7uTfHEf/G52kRFQt36740sPwx1ccKALcX1/kgmQw1aN8tkJ5S03xpihQ3 gfygSZ4gnjOAsuW6UW6t0+4tNJjp9TY+5J67i+kf6OLnh2zxTC1gPYKDENPDTYFvwu/6 3d8Q== X-Gm-Message-State: AMCzsaUk/WuTuv40NYHHNTSsbyAMdn8kfwrl+v/hQDlpfhH7g4kctVZ9 Ke0z65FE39wpHRYURbxze/Ylb89r6UY= X-Google-Smtp-Source: ABhQp+Qb2llYXtihFFvUGJqIw6nGToQsv4kCeVyhsYH/ZYMTjG/uHOLLeulVvp71tarpycFaArLplw== X-Received: by 10.84.157.74 with SMTP id u10mr5431710plu.402.1508541653868; Fri, 20 Oct 2017 16:20:53 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-165-104.tukw.qwest.net. [97.113.165.104]) by smtp.gmail.com with ESMTPSA id a17sm3532594pfk.173.2017.10.20.16.20.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Oct 2017 16:20:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 20 Oct 2017 16:19:50 -0700 Message-Id: <20171020232023.15010-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171020232023.15010-1-richard.henderson@linaro.org> References: <20171020232023.15010-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v7 19/52] tcg: Remove TCGV_EQUAL* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, cota@braap.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP When we used structures for TCGv_*, we needed a macro in order to perform a comparison. Now that we use pointers, this is just clutter. Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daudé --- tcg/tcg-op.h | 6 ++---- tcg/tcg.h | 4 ---- target/cris/translate.c | 6 +++--- target/i386/translate.c | 6 +++--- target/m68k/translate.c | 2 +- target/ppc/translate.c | 4 ++-- 6 files changed, 11 insertions(+), 17 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index ab2f3c6cee..3129159907 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -328,7 +328,7 @@ static inline void tcg_gen_discard_i32(TCGv_i32 arg) static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) { - if (!TCGV_EQUAL_I32(ret, arg)) { + if (ret != arg) { tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); } } @@ -522,7 +522,7 @@ static inline void tcg_gen_discard_i64(TCGv_i64 arg) static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) { - if (!TCGV_EQUAL_I64(ret, arg)) { + if (ret != arg) { tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); } } @@ -809,7 +809,6 @@ void tcg_gen_lookup_and_goto_ptr(void); #define tcg_temp_free tcg_temp_free_i32 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x) #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x) -#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b) #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else @@ -820,7 +819,6 @@ void tcg_gen_lookup_and_goto_ptr(void); #define tcg_temp_free tcg_temp_free_i64 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x) #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x) -#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b) #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 #endif diff --git a/tcg/tcg.h b/tcg/tcg.h index b7fac0db8a..8f692bc6cf 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -428,10 +428,6 @@ typedef TCGv_ptr TCGv_env; #error Unhandled TARGET_LONG_BITS value #endif -#define TCGV_EQUAL_I32(a, b) ((a) == (b)) -#define TCGV_EQUAL_I64(a, b) ((a) == (b)) -#define TCGV_EQUAL_PTR(a, b) ((a) == (b)) - /* Dummy definition to avoid compiler warnings. */ #define TCGV_UNUSED_I32(x) (x = (TCGv_i32)-1) #define TCGV_UNUSED_I64(x) (x = (TCGv_i64)-1) diff --git a/target/cris/translate.c b/target/cris/translate.c index 38a999e6f1..55a9202777 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -839,7 +839,7 @@ static void cris_alu(DisasContext *dc, int op, } tcg_gen_or_tl(d, d, tmp); } - if (!TCGV_EQUAL(tmp, d)) { + if (tmp != d) { tcg_temp_free(tmp); } } @@ -1162,7 +1162,7 @@ static inline void t_gen_sext(TCGv d, TCGv s, int size) tcg_gen_ext8s_i32(d, s); } else if (size == 2) { tcg_gen_ext16s_i32(d, s); - } else if (!TCGV_EQUAL(d, s)) { + } else { tcg_gen_mov_tl(d, s); } } @@ -1173,7 +1173,7 @@ static inline void t_gen_zext(TCGv d, TCGv s, int size) tcg_gen_ext8u_i32(d, s); } else if (size == 2) { tcg_gen_ext16u_i32(d, s); - } else if (!TCGV_EQUAL(d, s)) { + } else { tcg_gen_mov_tl(d, s); } } diff --git a/target/i386/translate.c b/target/i386/translate.c index 5f24a2de3c..d6697f721c 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -742,7 +742,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) size = s->cc_op - CC_OP_SUBB; t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); /* If no temporary was used, be careful not to alias t1 and t0. */ - t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; + t0 = t1 == cpu_cc_src ? cpu_tmp0 : reg; tcg_gen_mov_tl(t0, cpu_cc_srcT); gen_extu(size, t0); goto add_sub; @@ -951,7 +951,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) break; case JCC_L: gen_compute_eflags(s); - if (TCGV_EQUAL(reg, cpu_cc_src)) { + if (reg == cpu_cc_src) { reg = cpu_tmp0; } tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ @@ -962,7 +962,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) default: case JCC_LE: gen_compute_eflags(s); - if (TCGV_EQUAL(reg, cpu_cc_src)) { + if (reg == cpu_cc_src) { reg = cpu_tmp0; } tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */ diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d738f32f9c..63b1552669 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -58,7 +58,7 @@ static TCGv_i64 cpu_macc[4]; #define QREG_SP get_areg(s, 7) static TCGv NULL_QREG; -#define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) +#define IS_NULL_QREG(t) (t == NULL_QREG) /* Used to distinguish stores from bad addressing modes. */ static TCGv store_dummy; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a81ff69d75..616cf8f50e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -902,7 +902,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, gen_set_Rc0(ctx, t0); } - if (!TCGV_EQUAL(t0, ret)) { + if (t0 != ret) { tcg_gen_mov_tl(ret, t0); tcg_temp_free(t0); } @@ -1438,7 +1438,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, gen_set_Rc0(ctx, t0); } - if (!TCGV_EQUAL(t0, ret)) { + if (t0 != ret) { tcg_gen_mov_tl(ret, t0); tcg_temp_free(t0); }