From patchwork Fri Dec 29 14:29:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 10137145 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 54B6C6020A for ; Fri, 29 Dec 2017 14:35:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4757E2DE56 for ; Fri, 29 Dec 2017 14:35:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B0122DF5B; Fri, 29 Dec 2017 14:35:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B315B2DE56 for ; Fri, 29 Dec 2017 14:35:19 +0000 (UTC) Received: from localhost ([::1]:42852 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUvkk-0003yu-PM for patchwork-qemu-devel@patchwork.kernel.org; Fri, 29 Dec 2017 09:35:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUvg6-0000Ca-0k for qemu-devel@nongnu.org; Fri, 29 Dec 2017 09:30:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eUvg5-0006G0-3V for qemu-devel@nongnu.org; Fri, 29 Dec 2017 09:30:30 -0500 Received: from iserv.reactos.org ([2a01:4f8:221:4c5::3]:38283) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eUvg4-0006AI-UP for qemu-devel@nongnu.org; Fri, 29 Dec 2017 09:30:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=reactos.org; s=25047; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=AoyjMdDDBbyTv/52IB1ODZzrLNtf/SJpuVK79P4u8Ws=; b=QBDkeNI9BQq8+6eK8QfMZ3tN/Zjs8XG9rvwjbTl0jXp/4tnkr3TM7zJyfjfVKkzUNnN01cju7SNAIZuebFJ/UHGEwsRLzKRsXrpmk8+4X/686l1uTUPclaPJE+MRWDmkJ3IJfJqc09eBboEc8hDfiRV2df7xgHogiqrHBV6WfYU=; Received: from [2a01:e34:ee6b:9c80:6267:20ff:fe65:a488] (helo=localhost.localdomain) by iserv.reactos.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1eUvfO-0002om-FS; Fri, 29 Dec 2017 14:29:46 +0000 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: Aurelien Jarno , Yongbok Kim , "Michael S . Tsirkin" , Paolo Bonzini , qemu-devel@nongnu.org Date: Fri, 29 Dec 2017 15:29:12 +0100 Message-Id: <20171229142922.31701-7-hpoussin@reactos.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171229142922.31701-1-hpoussin@reactos.org> References: <20171229142922.31701-1-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a01:4f8:221:4c5::3 Subject: [Qemu-devel] [PATCH v3 06/16] piix4: add Reset Control Register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Signed-off-by: Hervé Poussineau --- hw/isa/piix4.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4f476dc7e6..7c83e7c23d 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2016 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +34,10 @@ PCIDevice *piix4_dev; typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -87,6 +92,30 @@ static const VMStateDescription vmstate_piix4 = { } }; +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s = opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + s->rcr = val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s = opaque; + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops = { + .read = piix4_rcr_read, + .write = piix4_rcr_write, + .endianness = DEVICE_LITTLE_ENDIAN +}; + static void piix4_realize(PCIDevice *pci, Error **errp) { DeviceState *dev = DEVICE(pci); @@ -96,6 +125,12 @@ static void piix4_realize(PCIDevice *pci, Error **errp) pci_address_space_io(pci), errp)) { return; } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(pci), 0xcf9, + &s->rcr_mem, 1); + piix4_dev = pci; qemu_register_reset(piix4_reset, s); }