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[193.232.173.35]) by smtp.gmail.com with ESMTPSA id u23sm1165901lje.79.2018.01.05.13.27.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jan 2018 13:27:04 -0800 (PST) Date: Sat, 6 Jan 2018 00:41:05 +0300 From: Antony Pavlov To: Michael Clark Message-Id: <20180106004105.281b992abcf939b0cf45b88f@gmail.com> In-Reply-To: <1514940265-18093-13-git-send-email-mjc@sifive.com> References: <1514940265-18093-1-git-send-email-mjc@sifive.com> <1514940265-18093-13-git-send-email-mjc@sifive.com> X-Mailer: Sylpheed 3.5.1 (GTK+ 2.24.25; i686-pc-linux-gnu) Mime-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: Re: [Qemu-devel] [PATCH v1 12/21] RISC-V HART Array X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , qemu-devel@nongnu.org, Sagar Karandikar Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP On Wed, 3 Jan 2018 13:44:16 +1300 Michael Clark wrote: > Holds the state of a heterogenous array of RISC-V hardware threads. ... > --- /dev/null > +++ b/include/hw/riscv/riscv_hart.h > @@ -0,0 +1,45 @@ > +/* > + * QEMU RISC-V Hart Array interface > + * > + * Copyright (c) 2017 SiFive, Inc. > + * > + * Holds the state of a heterogenous array of RISC-V harts > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef HW_RISCV_HART_H > +#define HW_RISCV_HART_H > + > +#define TYPE_RISCV_HART_ARRAY "riscv.hart_array" > + > +#define RISCV_HART_ARRAY(obj) \ > + OBJECT_CHECK(RISCVHartArrayState, (obj), TYPE_RISCV_HART_ARRAY) > + > +typedef struct RISCVHartArrayState { > + /*< private >*/ > + SysBusDevice parent_obj; > + > + /*< public >*/ > + uint32_t num_harts; > + char *cpu_model; > + RISCVCPU *harts; > +} RISCVHartArrayState; > + > +#endif > -- > 2.7.0 Hmm, you use SysBusDevice, uint32_t and RISCVCPU types but there is no header files inclusion to define these types. I propose this fixup: Some files in include/hw/riscv/ are affected by this problem (e.g. sifive_uart.h). --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -27,6 +27,10 @@ #ifndef HW_RISCV_HART_H #define HW_RISCV_HART_H +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" + #define TYPE_RISCV_HART_ARRAY "riscv.hart_array" #define RISCV_HART_ARRAY(obj) \