From patchwork Thu May 3 06:21:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 10377107 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0DF2260327 for ; Thu, 3 May 2018 06:27:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F291529038 for ; Thu, 3 May 2018 06:27:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E733E29067; Thu, 3 May 2018 06:27:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3A53129038 for ; Thu, 3 May 2018 06:27:32 +0000 (UTC) Received: from localhost ([::1]:54200 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7iF-000320-E2 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 03 May 2018 02:27:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE7dL-0007c9-QN for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE7dH-0002bm-H9 for qemu-devel@nongnu.org; Thu, 03 May 2018 02:22:27 -0400 Received: from ozlabs.org ([203.11.71.1]:56543) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE7dG-0002ZZ-TN; Thu, 03 May 2018 02:22:23 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40c4mZ1Djcz9s4q; Thu, 3 May 2018 16:21:49 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1525328510; bh=RFN7eQLrLTOlb5OPnXdK03zjkFg1+sueMJmp0B2TlTI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aluqE62dn1xkaSPV5LcauNUEqyteVt6LKuAb7gJ1tQf0lhtKJ8sBtD+k+5jUyLCZD bPBxAhMLy3rkVKcD/3+NCuNakU3OLpJjafFJrSfh0jD0nQ1rlGgXKHr4lOh3AYyRAF eLQEh0oMZvfzRuwdFU0soqvCOruFl5CT90nNNIXA= From: David Gibson To: groug@kaod.org, clg@kaod.org Date: Thu, 3 May 2018 16:21:41 +1000 Message-Id: <20180503062145.17899-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503062145.17899-1-david@gibson.dropbear.id.au> References: <20180503062145.17899-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH 4/8] spapr: Make a helper to set up cpu entry point state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Under PAPR, only the boot CPU is active when the system starts. Other cpus must be explicitly activated using an RTAS call. The entry state for the boot and secondary cpus isn't identical, but it has some things in common. We're going to add a bit more common setup later, too, so to simplify make a helper which sets up the common entry state for both boot and secondary cpu threads. Signed-off-by: David Gibson Signed-off-by: Cédric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 4 +--- hw/ppc/spapr_cpu_core.c | 9 +++++++++ hw/ppc/spapr_rtas.c | 6 ++---- include/hw/ppc/spapr_cpu_core.h | 3 +++ 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b35aff5d81..944bee7a71 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1668,10 +1668,8 @@ static void spapr_machine_reset(void) g_free(fdt); /* Set up the entry state */ - first_ppc_cpu->env.gpr[3] = fdt_addr; + spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); first_ppc_cpu->env.gpr[5] = 0; - first_cpu->halted = 0; - first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; spapr->cas_reboot = false; } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 01dbc69424..a98c7b04c6 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -52,6 +52,15 @@ static void spapr_cpu_reset(void *opaque) } +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3) +{ + CPUPPCState *env = &cpu->env; + + env->nip = nip; + env->gpr[3] = r3; + CPU(cpu)->halted = 0; +} + static void spapr_cpu_destroy(PowerPCCPU *cpu) { qemu_unregister_reset(spapr_cpu_reset, cpu); diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index df073447c5..840d198a8d 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -37,6 +37,7 @@ #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" #include "hw/ppc/spapr_rtas.h" +#include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/ppc.h" #include "hw/boards.h" @@ -173,10 +174,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRMachineState *spapr, */ newcpu->env.tb_env->tb_offset = callcpu->env.tb_env->tb_offset; - env->nip = start; - env->gpr[3] = r3; - - CPU(newcpu)->halted = 0; + spapr_cpu_set_entry_state(newcpu, start, r3); qemu_cpu_kick(CPU(newcpu)); diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h index 1129f344aa..47dcfda12b 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -12,6 +12,7 @@ #include "hw/qdev.h" #include "hw/cpu/core.h" #include "target/ppc/cpu-qom.h" +#include "target/ppc/cpu.h" #define TYPE_SPAPR_CPU_CORE "spapr-cpu-core" #define SPAPR_CPU_CORE(obj) \ @@ -38,4 +39,6 @@ typedef struct sPAPRCPUCoreClass { } sPAPRCPUCoreClass; const char *spapr_get_cpu_core_type(const char *cpu_type); +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3); + #endif