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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id e28-v6sm503040ljb.92.2018.05.16.11.52.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 11:52:24 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 20:51:31 +0200 Message-Id: <20180516185146.30708-24-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180516185146.30708-1-edgar.iglesias@gmail.com> References: <20180516185146.30708-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH v3 23/38] target-microblaze: Implement MFSE EAR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: "Edgar E. Iglesias" Implement MFSE EAR to enable access to the upper part of EAR. Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 76f09e3f7e..03a0289858 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -459,7 +459,7 @@ static void dec_msr(DisasContext *dc) CPUState *cs = CPU(dc->cpu); TCGv_i32 t0, t1; unsigned int sr, rn; - bool to, clrset; + bool to, clrset, extended; sr = extract32(dc->imm, 0, 14); to = extract32(dc->imm, 14, 1); @@ -467,6 +467,9 @@ static void dec_msr(DisasContext *dc) dc->type_b = 1; if (to) { dc->cpustate_changed = 1; + extended = extract32(dc->imm, 24, 1); + } else { + extended = extract32(dc->imm, 19, 1); } /* msrclr and msrset. */ @@ -559,6 +562,10 @@ static void dec_msr(DisasContext *dc) msr_read(dc, cpu_R[dc->rd]); break; case SR_EAR: + if (extended) { + tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); + break; + } case SR_ESR: case SR_FSR: case SR_BTR: