diff mbox

[4/4] bochs-display: add pcie support

Message ID 20180517092513.735-5-kraxel@redhat.com (mailing list archive)
State New, archived
Headers show

Commit Message

Gerd Hoffmann May 17, 2018, 9:25 a.m. UTC 
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 hw/display/bochs-display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Marc-André Lureau May 18, 2018, 3:13 p.m. UTC | #1 
Hi

On Thu, May 17, 2018 at 11:25 AM, Gerd Hoffmann <kraxel@redhat.com> wrote:
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---

Could you explain where the 0x80 offset comes from?


>  hw/display/bochs-display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c
> index 9ea6f798f4..23dbf57b8f 100644
> --- a/hw/display/bochs-display.c
> +++ b/hw/display/bochs-display.c
> @@ -254,6 +254,7 @@ static void bochs_display_realize(PCIDevice *dev, Error **errp)
>  {
>      BochsDisplayState *s = BOCHS_DISPLAY(dev);
>      Object *obj = OBJECT(dev);
> +    int ret;
>
>      s->con = graphic_console_init(DEVICE(dev), 0, &bochs_display_gfx_ops, s);
>
> @@ -280,6 +281,12 @@ static void bochs_display_realize(PCIDevice *dev, Error **errp)
>      pci_register_bar(&s->pci, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
>      pci_register_bar(&s->pci, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
>
> +    if (pci_bus_is_express(pci_get_bus(dev))) {
> +        dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
> +        ret = pcie_endpoint_cap_init(dev, 0x80);
> +        assert(ret > 0);
> +    }
> +
>      memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
>  }
>
> @@ -341,6 +348,7 @@ static const TypeInfo bochs_display_type_info = {
>      .instance_init  = bochs_display_init,
>      .class_init     = bochs_display_class_init,
>      .interfaces     = (InterfaceInfo[]) {
> +        { INTERFACE_PCIE_DEVICE },
>          { INTERFACE_CONVENTIONAL_PCI_DEVICE },
>          { },
>      },
> --
> 2.9.3
>
>
Gerd Hoffmann May 22, 2018, 9:33 a.m. UTC | #2 
On Fri, May 18, 2018 at 05:13:27PM +0200, Marc-André Lureau wrote:
> Hi
> 
> On Thu, May 17, 2018 at 11:25 AM, Gerd Hoffmann <kraxel@redhat.com> wrote:
> > Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> > ---
> 
> Could you explain where the 0x80 offset comes from?

Pulled out of thin air.  Standard pci cfg space header size is 0x40, so
it must be between 0x40 and 0xff - sizeof(capability).  And it must not
overlap with other pci(e) capabilities (easy as this is the only one).
That are the only constrains I'm aware of.

cheers,
  Gerd
diff mbox

Patch

diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c
index 9ea6f798f4..23dbf57b8f 100644
--- a/hw/display/bochs-display.c
+++ b/hw/display/bochs-display.c
@@ -254,6 +254,7 @@  static void bochs_display_realize(PCIDevice *dev, Error **errp)
 {
     BochsDisplayState *s = BOCHS_DISPLAY(dev);
     Object *obj = OBJECT(dev);
+    int ret;
 
     s->con = graphic_console_init(DEVICE(dev), 0, &bochs_display_gfx_ops, s);
 
@@ -280,6 +281,12 @@  static void bochs_display_realize(PCIDevice *dev, Error **errp)
     pci_register_bar(&s->pci, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
     pci_register_bar(&s->pci, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
 
+    if (pci_bus_is_express(pci_get_bus(dev))) {
+        dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
+        ret = pcie_endpoint_cap_init(dev, 0x80);
+        assert(ret > 0);
+    }
+
     memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
 }
 
@@ -341,6 +348,7 @@  static const TypeInfo bochs_display_type_info = {
     .instance_init  = bochs_display_init,
     .class_init     = bochs_display_class_init,
     .interfaces     = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
         { },
     },