| Message ID | 20180612051630.17854-1-sjitindarsingh@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jun 12, 2018 at 03:16:29PM +1000, Suraj Jitindar Singh wrote: > For cap_ppc_safe_cache to be set to workaround, we require both a l1d > cache flush instruction and private l1d cache. > > On POWER8 don't require private l1d cache. This means a guest on a > POWER8 machine can make use of the cache flush workarounds. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Applied to ppc-for-3.0, thanks. > > --- > > V1 -> V2: > - Use mfpvr() to detect host type > > --- > target/ppc/kvm.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c > index 2c0c34e125..7fe9d0126b 100644 > --- a/target/ppc/kvm.c > +++ b/target/ppc/kvm.c > @@ -2412,11 +2412,28 @@ bool kvmppc_has_cap_mmu_hash_v3(void) > return cap_mmu_hash_v3; > } > > +static bool kvmppc_power8_host(void) > +{ > + bool ret = false; > +#ifdef TARGET_PPC64 > + { > + uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); > + ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || > + (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || > + (base_pvr == CPU_POWERPC_POWER8_BASE); > + } > +#endif /* TARGET_PPC64 */ > + return ret; > +} > + > static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) > { > + bool l1d_thread_priv_req = !kvmppc_power8_host(); > + > if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { > return 2; > - } else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && > + } else if ((!l1d_thread_priv_req || > + c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && > (c.character & c.character_mask > & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { > return 1;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 2c0c34e125..7fe9d0126b 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2412,11 +2412,28 @@ bool kvmppc_has_cap_mmu_hash_v3(void) return cap_mmu_hash_v3; } +static bool kvmppc_power8_host(void) +{ + bool ret = false; +#ifdef TARGET_PPC64 + { + uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); + ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || + (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || + (base_pvr == CPU_POWERPC_POWER8_BASE); + } +#endif /* TARGET_PPC64 */ + return ret; +} + static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) { + bool l1d_thread_priv_req = !kvmppc_power8_host(); + if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { return 2; - } else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && + } else if ((!l1d_thread_priv_req || + c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && (c.character & c.character_mask & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { return 1;
For cap_ppc_safe_cache to be set to workaround, we require both a l1d cache flush instruction and private l1d cache. On POWER8 don't require private l1d cache. This means a guest on a POWER8 machine can make use of the cache flush workarounds. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> --- V1 -> V2: - Use mfpvr() to detect host type --- target/ppc/kvm.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)