diff mbox

[v2] target/arm: Forbid unprivileged mode for M Baseline

Message ID 20180705222622.17139-1-jusual@mail.ru (mailing list archive)
State New, archived
Headers show

Commit Message

Denis V. Lunev" via July 5, 2018, 10:26 p.m. UTC 
MSR handling is the only place where CONTROL.nPRIV is modified.

Signed-off-by: Julia Suvorova <jusual@mail.ru>
---
v2:
    * Add the check in the CONTROL_NS case

 target/arm/helper.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

Comments

Peter Maydell July 6, 2018, 2:15 p.m. UTC | #1 
On 5 July 2018 at 23:26, Julia Suvorova <jusual@mail.ru> wrote:
> MSR handling is the only place where CONTROL.nPRIV is modified.
>
> Signed-off-by: Julia Suvorova <jusual@mail.ru>
> ---
> v2:
>     * Add the check in the CONTROL_NS case
>
>  target/arm/helper.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

As we're now in freeze for the QEMU 3.0 release, I've added this
patch to a branch I'm keeping with arm-related patches intended
to go into 3.1. You can find it at
https://git.linaro.org/people/peter.maydell/qemu-arm.git target-arm.for-3.1
but note that it will be rebased in future so be careful
if you base anything on it. (You might find it easier to just
ignore it ;-))

thanks
-- PMM
diff mbox

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5ee229eb35..2343aa5069 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10686,8 +10686,10 @@  void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
             write_v7m_control_spsel_for_secstate(env,
                                                  val & R_V7M_CONTROL_SPSEL_MASK,
                                                  M_REG_NS);
-            env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
-            env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
+            if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
+                env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
+                env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
+            }
             return;
         case 0x98: /* SP_NS */
         {
@@ -10781,8 +10783,10 @@  void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
             !arm_v7m_is_handler_mode(env)) {
             write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
         }
-        env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
-        env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
+        if (arm_feature(env, ARM_FEATURE_M_MAIN)) {
+            env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
+            env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
+        }
         break;
     default:
     bad_reg: