From patchwork Mon Jul 9 14:35:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 10514775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B7EF66032A for ; Mon, 9 Jul 2018 14:37:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A91322894C for ; Mon, 9 Jul 2018 14:37:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C92D2899D; Mon, 9 Jul 2018 14:37:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 218A82894C for ; Mon, 9 Jul 2018 14:37:10 +0000 (UTC) Received: from localhost ([::1]:42420 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcXHp-0006Rk-CC for patchwork-qemu-devel@patchwork.kernel.org; Mon, 09 Jul 2018 10:37:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57765) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcXH4-00067W-27 for qemu-devel@nongnu.org; Mon, 09 Jul 2018 10:36:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcXH3-0001aB-6y for qemu-devel@nongnu.org; Mon, 09 Jul 2018 10:36:22 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:47551) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fcXGx-0001YK-V3; Mon, 09 Jul 2018 10:36:16 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 8F9DE21D06; Mon, 9 Jul 2018 10:36:12 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 09 Jul 2018 10:36:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:message-id:subject:to:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=EBCn/hJk+WmfZ76FjsmOieyb7LhkQdRZ5d/hcjM+R a8=; b=N/WVvqFw7ohFX2XkfYSBeodmCQNaTi44B6uwbJIVOjwof7igKykSElk3s IgD1MGssXONSKFDnIPYX8GVZhGiNlk6f+I3guEA39W1tRp0LzAE3E6B1R7E2nZwf lPOueisNgZyLUB8z4odI2W8odnI1LX5FznsyMQtWvWRyY/tUBGE3mnFw6bO5o9ZF 7c2kRkEJ2NY9YhFP++sKEG97pd0x0frWZEE3Gmuyt3mMWlnj7KhDe+5fVFwvHFJv pYG4sTeft9tA6t5yiH1IAcTgbVavNt8AKYTcP8FfxnTQnG4ynXAzUjVO0AaFx/+y 26nj9fl8upZxO359nAxv4K1/1zCHQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:message-id:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; bh=EBCn/hJk+WmfZ76Fj smOieyb7LhkQdRZ5d/hcjM+Ra8=; b=fw3KakZt16haJREGbiLjTULPs70rRBYAo gMiMHwzOP/Vf30gTDjNMXDCv0e6STKAarwxiPw1HpXW7/0qjl/lAehtbhxmHmMf2 /FQcfhQT5YKDUttpVZhuaYNZob0Eb7ZtdbqmBaiuIZvb+DDHNvbaEWYj2ttcSCXE 8lF1y/+jpslIHg2eFGftZ1W9q6xOVngYClRQRTKI5wRLo8Oo9+DRreUwEGUCJsRP CSYx8MAk4mgKmASpigl02VBpntO1csaHGxVNaGFQY7k1++XACvKFj0EnX4Tp2GLj Lym9cOSLuanSB2PeGmwvfr08VZu8cRAZN+n/w4ORpDzU+xJ3iuKhQ== X-ME-Proxy: X-ME-Sender: Received: from localhost.localdomain (ppp118-210-173-37.bras2.adl6.internode.on.net [118.210.173.37]) by mail.messagingengine.com (Postfix) with ESMTPA id F38D71029E; Mon, 9 Jul 2018 10:36:08 -0400 (EDT) From: Andrew Jeffery To: qemu-devel@nongnu.org Date: Tue, 10 Jul 2018 00:05:24 +0930 Message-Id: <20180709143524.17480-1-andrew@aj.id.au> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH] aspeed: Implement write-1-{set, clear} for AST2500 strapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Andrew Jeffery , openbmc@lists.ozlabs.org, qemu-arm@nongnu.org, joel@jms.id.au, clg@kaod.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The AST2500 SoC family changes the runtime behaviour of the hardware strapping register (SCU70) to write-1-set/write-1-clear, with write-1-clear implemented on the "read-only" SoC revision register (SCU7C). For the the AST2400, the hardware strapping is runtime-configured with read-modify-write semantics. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley --- hw/misc/aspeed_scu.c | 19 +++++++++++++++++-- include/hw/misc/aspeed_scu.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 5e6d5744eeca..9051767cbbcd 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -202,11 +202,26 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, case PROT_KEY: s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; return; - + case HW_STRAP1: + if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { + s->regs[HW_STRAP1] |= data; + return; + } + /* Jump to assignment below */ + break; + case SILICON_REV: + if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { + s->regs[HW_STRAP1] &= ~data; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + /* Avoid assignment below, we've handled everything */ + return; case FREQ_CNTR_EVAL: case VGA_SCRATCH1 ... VGA_SCRATCH8: case RNG_DATA: - case SILICON_REV: case FREE_CNTR4: case FREE_CNTR4_EXT: qemu_log_mask(LOG_GUEST_ERROR, diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index d70cc0aeca61..169611a211bb 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -37,6 +37,8 @@ typedef struct AspeedSCUState { #define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A1_SILICON_REV 0x04010303U +#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) + extern bool is_supported_silicon_rev(uint32_t silicon_rev); #define ASPEED_SCU_PROT_KEY 0x1688A8A8