From patchwork Tue Jul 10 15:33:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhijian Li (Fujitsu)\" via" X-Patchwork-Id: 10517225 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2006E6020F for ; Tue, 10 Jul 2018 15:50:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1F1429342 for ; Tue, 10 Jul 2018 15:50:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF7592933E; Tue, 10 Jul 2018 15:50:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E3F942931E for ; Tue, 10 Jul 2018 15:50:17 +0000 (UTC) Received: from localhost ([::1]:48490 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcuu9-0002W6-0i for patchwork-qemu-devel@patchwork.kernel.org; Tue, 10 Jul 2018 11:50:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcuec-0005kJ-EG for qemu-devel@nongnu.org; Tue, 10 Jul 2018 11:34:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcueX-0005Jq-Dz for qemu-devel@nongnu.org; Tue, 10 Jul 2018 11:34:14 -0400 Received: from smtp38.i.mail.ru ([94.100.177.98]:37930) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fcueX-0005Ix-1B for qemu-devel@nongnu.org; Tue, 10 Jul 2018 11:34:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=Message-Id:Date:Subject:Cc:To:From; bh=p3/p4NKG0/JD7Qb15YS11jlUGGJoHntlqbCCQQj4wiY=; b=AWYyBwIDacmw+JWErPx5jTE+JxYNAjc5yc2tQTou1Tp+im9VWLdcak4AHbCYe9JYCRUpnE7080V7cZ2oo7PcorXsqVnXPorXSKqcm1AHyFrNBFtLmtlQWLY6y1L4RRiHNwZ43TaTqlsOhWWukw2BQ5ELj2rqdfMsk8tFebXo3yo=; Received: by smtp38.i.mail.ru with esmtpa (envelope-from ) id 1fcueT-0003rG-3F; Tue, 10 Jul 2018 18:34:05 +0300 To: qemu-devel@nongnu.org Date: Tue, 10 Jul 2018 18:33:35 +0300 Message-Id: <20180710153335.1232-1-jusual@mail.ru> X-Mailer: git-send-email 2.17.1 Authentication-Results: smtp38.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A500A81A939F66F6A4E74E3D43FA743BCF9351908423F8223F0A6AB1C7CE11FEE3EB7D890E3377C531BA3038C0950A5D36B5C8C57E37DE458B4C7702A67D5C33162DBA43225CD8A89F9FFED5BD9FB417550F3BCBF6750655CA97B992760CC29D5F43847C11F186F3C5E7DDDDC251EA7DABCC89B49CDF41148FFC2B27DE93B9EBF03B503F486389A921A5CC5B56E945C8DA X-Mailru-Sender: 3BB5BBD94288672347CC171B42989A243BA6788AFC7166F09C589BA6E31080D4CAE43C95141D0C847C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.177.98 Subject: [Qemu-devel] [PATCH] nvic: Change NVIC to support ARMv6-M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Julia Suvorova via Qemu-devel From: "Zhijian Li (Fujitsu)\" via" Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Stefan Hajnoczi , Julia Suvorova Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The differences from ARMv7-M NVIC are: * ARMv6-M only supports up to 32 external interrupts (configurable feature already). The ICTR is reserved. * Active Bit Register is reserved. * ARMv6-M supports 4 priority levels against 256 in ARMv7-M. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 38aaf3dc8e..8545c87caa 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -420,6 +420,10 @@ static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio) assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */ assert(irq < s->num_irq); + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { + prio &= 0xc0; + } + if (secure) { assert(exc_is_banked(irq)); s->sec_vectors[irq].prio = prio; @@ -777,6 +781,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) switch (offset) { case 4: /* Interrupt Control Type. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { + goto bad_offset; + } return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; case 0xc: /* CPPWR */ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { @@ -850,7 +857,10 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd08: /* Vector Table Offset. */ return cpu->env.v7m.vecbase[attrs.secure]; case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */ - val = 0xfa050000 | (s->prigroup[attrs.secure] << 8); + val = 0xfa050000; + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + val |= (s->prigroup[attrs.secure] << 8); + } if (attrs.secure) { /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */ val |= cpu->env.v7m.aircr; @@ -1274,6 +1284,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, "Setting VECTRESET when not in DEBUG mode " "is UNPREDICTABLE\n"); } + if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { + nvic_irq_update(s); + break; + } s->prigroup[attrs.secure] = extract32(value, R_V7M_AIRCR_PRIGROUP_SHIFT, R_V7M_AIRCR_PRIGROUP_LENGTH); @@ -1785,6 +1799,11 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, break; case 0x300 ... 0x33f: /* NVIC Active */ val = 0; + + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { + break; + } + startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { @@ -2160,13 +2179,15 @@ static Property props_nvic[] = { static void armv7m_nvic_reset(DeviceState *dev) { - int resetprio; + int resetprio, resetprigroup; NVICState *s = NVIC(dev); memset(s->vectors, 0, sizeof(s->vectors)); memset(s->sec_vectors, 0, sizeof(s->sec_vectors)); - s->prigroup[M_REG_NS] = 0; - s->prigroup[M_REG_S] = 0; + + resetprigroup = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 0 : 5; + s->prigroup[M_REG_NS] = resetprigroup; + s->prigroup[M_REG_S] = resetprigroup; s->vectors[ARMV7M_EXCP_NMI].enabled = 1; /* MEM, BUS, and USAGE are enabled through