From patchwork Wed Jul 18 10:48:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 10532059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2F13660547 for ; Wed, 18 Jul 2018 10:51:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E5D828E76 for ; Wed, 18 Jul 2018 10:51:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2381228F85; Wed, 18 Jul 2018 10:51:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 727FD28E76 for ; Wed, 18 Jul 2018 10:51:18 +0000 (UTC) Received: from localhost ([::1]:35869 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ffk3B-0004vC-QK for patchwork-qemu-devel@patchwork.kernel.org; Wed, 18 Jul 2018 06:51:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36228) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ffk0l-0003Lk-UA for qemu-devel@nongnu.org; Wed, 18 Jul 2018 06:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ffk0i-0007jd-VD for qemu-devel@nongnu.org; Wed, 18 Jul 2018 06:48:47 -0400 Received: from ssl.serverraum.org ([2a01:4f8:151:8464::1:2]:58513) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ffk0i-0007j7-Ls for qemu-devel@nongnu.org; Wed, 18 Jul 2018 06:48:44 -0400 Received: from mwalle01.sab.local. (unknown [213.135.10.150]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 77C2E22DE3; Wed, 18 Jul 2018 12:48:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1531910923; bh=g67hZ8raEZ72Aq3VH108LmuOhzUTjEAMI4NrHQ9uIJQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y2RgnrUp7x/hirsF3XVVSO/2LhlW6vekl+ttGtbL0VCkRxOHPpDImqxEKzWlnDKav MxyAC7U3rykhBqLnpAiJswHIp4UOwlqGH/KOdgrAb/NgTW1df5hmVTLCs3R4G7lgz4 g5wBrKRv06RFj1OeqYXptG7xubgocc14UmjjwEd8= From: Michael Walle To: qemu-devel@nongnu.org Date: Wed, 18 Jul 2018 12:48:36 +0200 Message-Id: <20180718104836.18488-3-michael@walle.cc> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180718104836.18488-1-michael@walle.cc> References: <20180718104836.18488-1-michael@walle.cc> X-Virus-Scanned: clamav-milter 0.100.0 at web X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a01:4f8:151:8464::1:2 Subject: [Qemu-devel] [PATCH 3/3] milkymist-pfpu: add qtests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Walle Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add initial tests which check basic computations and error cases on the PFPU. Signed-off-by: Michael Walle --- MAINTAINERS | 1 + hw/lm32/lm32.h | 2 + tests/Makefile.include | 4 + tests/milkymist-pfpu-test.c | 193 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 200 insertions(+) create mode 100644 tests/milkymist-pfpu-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 666e936812..bde0d132b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -171,6 +171,7 @@ F: hw/*/milkymist-* F: include/hw/char/lm32_juart.h F: include/hw/lm32/ F: tests/tcg/lm32/ +F: tests/milkymist-* M68K M: Laurent Vivier diff --git a/hw/lm32/lm32.h b/hw/lm32/lm32.h index d1514a61b3..b14f7ce158 100644 --- a/hw/lm32/lm32.h +++ b/hw/lm32/lm32.h @@ -9,6 +9,8 @@ static inline DeviceState *lm32_pic_init(qemu_irq cpu_irq) SysBusDevice *d; dev = qdev_create(NULL, "lm32-pic"); + object_property_add_child(qdev_get_machine(), "lm32-pic", OBJECT(dev), + NULL); qdev_init_nofail(dev); d = SYS_BUS_DEVICE(dev); sysbus_connect_irq(d, 0, cpu_irq); diff --git a/tests/Makefile.include b/tests/Makefile.include index a49282704e..d02d673f7d 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -406,6 +406,8 @@ check-qtest-s390x-y += tests/virtio-console-test$(EXESUF) check-qtest-s390x-y += tests/virtio-serial-test$(EXESUF) check-qtest-s390x-y += tests/cpu-plug-test$(EXESUF) +check-qtest-lm32-y = tests/milkymist-pfpu-test$(EXESUF) + check-qtest-generic-y += tests/machine-none-test$(EXESUF) check-qtest-generic-y += tests/qom-test$(EXESUF) check-qtest-generic-y += tests/test-hmp$(EXESUF) @@ -868,6 +870,8 @@ tests/migration/initrd-stress.img: tests/migration/stress$(EXESUF) rm $(INITRD_WORK_DIR)/init rmdir $(INITRD_WORK_DIR) +tests/milkymist-pfpu-test$(EXESUF): tests/milkymist-pfpu-test.o + ifeq ($(CONFIG_POSIX),y) LIBS += -lutil endif diff --git a/tests/milkymist-pfpu-test.c b/tests/milkymist-pfpu-test.c new file mode 100644 index 0000000000..da506bbdf8 --- /dev/null +++ b/tests/milkymist-pfpu-test.c @@ -0,0 +1,193 @@ +/* + * QTest testcase for the Milkymist PFPU + * + * Copyright (c) 2018 Michael Walle + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "libqtest.h" + +#define PFPU_BASE 0x60006000 +#define PFPU_IRQ 8 + +static void pfpu_load_microcode(uint32_t *insn, int len) +{ + uint32_t addr = PFPU_BASE + 0x800; + while (len) { + writel(addr, *insn); + insn++; + len--; + addr += 4; + } +} + +static void pfpu_clear_microcode(void) +{ + uint32_t addr = PFPU_BASE + 0x800; + uint32_t len = 512; + while (len) { + writel(addr, 0); + len--; + addr += 4; + } +} + +static uint32_t float_to_u32(float val) +{ + return (*((uint32_t *)&(val))); +} + +static void pfpu_add(void) +{ + static uint32_t ucode[] = { + 0x000c2080, /* FADD R3, R4 */ + 0x00000000, /* NOP */ + 0x00000000, /* NOP */ + 0x00000000, /* NOP */ + 0x00000000, /* NOP */ + 0x00000003, /* NOP | EXIT R3 */ + 0x000c2380 /* VECTOUT R3, R4 */ + }; + + /* 2x1 mesh size */ + writel(PFPU_BASE + 0x8, 1); + writel(PFPU_BASE + 0xc, 0); + + /* write test operands to r3 and r4 */ + writel(PFPU_BASE + 0x40c, float_to_u32(3.0f)); + writel(PFPU_BASE + 0x410, float_to_u32(9.0f)); + + pfpu_load_microcode(ucode, ARRAY_SIZE(ucode)); + + /* dma base */ + writel(PFPU_BASE + 0x4, 0x40000000); + + /* start */ + writel(PFPU_BASE, 1); + + /* on a successful run, the busy flag should be cleared */ + g_assert(readl(PFPU_BASE) == 0); + + /* interrupt line should have been pulsed */ + g_assert(get_irq_latched(PFPU_IRQ) == 1); + clear_irq_latch(PFPU_IRQ); + g_assert(get_irq_latched(PFPU_IRQ) == 0); + + /* resulting vertices should be written to RAM */ + g_assert(readl(0x40000000) == float_to_u32(12.0f)); + g_assert(readl(0x40000004) == float_to_u32(9.0f)); + g_assert(readl(0x40000008) == float_to_u32(21.0f)); + g_assert(readl(0x4000000c) == float_to_u32(9.0f)); + + /* count of computed vertices */ + g_assert(readl(PFPU_BASE + 0x14) == 2); + + /* no collisions */ + g_assert(readl(PFPU_BASE + 0x18) == 0); + + /* no stray writes */ + g_assert(readl(PFPU_BASE + 0x1c) == 0); +} + +static void pfpu_microcode_overflow(void) +{ + /* 1x1 mesh size */ + writel(PFPU_BASE + 0x8, 1); + writel(PFPU_BASE + 0xc, 0); + + pfpu_clear_microcode(); + + /* start */ + writel(PFPU_BASE, 1); + + /* because there is no VECTOUT, the busy flag should not be cleared */ + g_assert(readl(PFPU_BASE) == 1); + + /* and there should be no pending interrupt */ + g_assert(get_irq_latched(PFPU_IRQ) == 0); +} + +static void pfpu_stray_writes(void) +{ + static uint32_t ucode[] = { + 0x000c0600, /* COPY R3 */ + 0x00000000, /* NOP */ + 0x00000000, /* NOP */ + 0x000c2380 /* VECTOUT R3, R4 */ + }; + + /* 1x1 mesh size */ + writel(PFPU_BASE + 0x8, 0); + writel(PFPU_BASE + 0xc, 0); + + /* write test operands to r3 and r4 */ + writel(PFPU_BASE + 0x40c, float_to_u32(1.0f)); + writel(PFPU_BASE + 0x410, float_to_u32(2.0f)); + + pfpu_load_microcode(ucode, ARRAY_SIZE(ucode)); + + /* dma base */ + writel(PFPU_BASE + 0x4, 0x40000000); + + /* start */ + writel(PFPU_BASE, 1); + clear_irq_latch(PFPU_IRQ); + + /* stray writes */ + g_assert(readl(PFPU_BASE + 0x1c) == 1); +} + +static void pfpu_collision(void) +{ + static uint32_t ucode[] = { + 0x000c0300, /* I2F R3 */ + 0x000c0600, /* COPY R3 */ + 0x00000000, /* NOP */ + 0x00000000, /* NOP */ + 0x000c2380 /* VECTOUT R3, R4 */ + }; + + /* 1x1 mesh size */ + writel(PFPU_BASE + 0x8, 0); + writel(PFPU_BASE + 0xc, 0); + + /* write test operands to r3 and r4 */ + writel(PFPU_BASE + 0x40c, float_to_u32(1.0f)); + writel(PFPU_BASE + 0x410, float_to_u32(2.0f)); + + pfpu_load_microcode(ucode, ARRAY_SIZE(ucode)); + + /* dma base */ + writel(PFPU_BASE + 0x4, 0x40000000); + + /* start */ + writel(PFPU_BASE, 1); + clear_irq_latch(PFPU_IRQ); + + /* collisions */ + g_assert(readl(PFPU_BASE + 0x18) == 1); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine milkymist"); + irq_intercept_in("lm32-pic"); + qtest_add_func("/milkymist-pfpu/add", pfpu_add); + qtest_add_func("/milkymist-pfpu/microcode-overflow", pfpu_microcode_overflow); + qtest_add_func("/milkymist-pfpu/collision", pfpu_collision); + qtest_add_func("/milkymist-pfpu/stray-writes", pfpu_stray_writes); + + ret = g_test_run(); + + qtest_end(); + + return ret; +}