From patchwork Fri Aug 31 11:15:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 10583631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5432A139B for ; Fri, 31 Aug 2018 11:29:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 582982B71D for ; Fri, 31 Aug 2018 11:29:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4AF582B858; Fri, 31 Aug 2018 11:29:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B4FC72B71D for ; Fri, 31 Aug 2018 11:29:03 +0000 (UTC) Received: from localhost ([::1]:53115 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvhbq-0003Kx-Ep for patchwork-qemu-devel@patchwork.kernel.org; Fri, 31 Aug 2018 07:29:02 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fvhVt-0005Hg-Hm for qemu-devel@nongnu.org; Fri, 31 Aug 2018 07:22:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fvhPX-0004eB-8H for qemu-devel@nongnu.org; Fri, 31 Aug 2018 07:16:23 -0400 Received: from 8.mo177.mail-out.ovh.net ([46.105.61.98]:56024) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fvhPX-0004dw-1Q for qemu-devel@nongnu.org; Fri, 31 Aug 2018 07:16:19 -0400 Received: from player714.ha.ovh.net (unknown [10.109.143.238]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id D6685C07FF for ; Fri, 31 Aug 2018 13:16:17 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10605-110.w90-89.abo.wanadoo.fr [90.89.196.110]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id 74C8D3C00C3; Fri, 31 Aug 2018 13:16:09 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-devel@nongnu.org Date: Fri, 31 Aug 2018 13:15:55 +0200 Message-Id: <20180831111555.15008-2-clg@kaod.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180831111555.15008-1-clg@kaod.org> References: <20180831103816.13479-1-clg@kaod.org> <20180831111555.15008-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2558326067414338368 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedtjedrhedtgdeflecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.61.98 Subject: [Qemu-devel] [PATCH 11/11] aspeed/smc: Add dummy data register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Andrew Jeffery , Alistair Francis , qemu-arm@nongnu.org, Joel Stanley , =?utf-8?q?C=C3=A9dric_L?= =?utf-8?q?e_Goater?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The SMC controllers have a register containing the byte that will be used as dummy output. It can be modified by software. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé --- hw/ssi/aspeed_smc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index da2fedfcd3cd..f31bbc895caa 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -102,8 +102,8 @@ /* Misc Control Register #1 */ #define R_MISC_CTRL1 (0x50 / 4) -/* Misc Control Register #2 */ -#define R_MISC_CTRL2 (0x54 / 4) +/* SPI dummy cycle data */ +#define R_DUMMY_DATA (0x54 / 4) /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) @@ -548,7 +548,7 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) */ if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { - ssi_transfer(fl->controller->spi, 0xFF); + ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); } } } @@ -680,6 +680,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == s->r_timings || addr == s->r_ce_ctrl || addr == R_INTR_CTRL || + addr == R_DUMMY_DATA || (s->ctrl->has_dma && addr == R_DMA_CTRL) || (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) || (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) || @@ -912,6 +913,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, } } else if (addr == R_INTR_CTRL) { s->regs[addr] = value; + } else if (addr == R_DUMMY_DATA) { + s->regs[addr] = value & 0xff ; } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) { aspeed_smc_dma_ctrl(s, value); } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) {