From patchwork Fri Sep 21 07:01:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 10609175 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E59B46CB for ; Fri, 21 Sep 2018 07:03:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D469528F87 for ; Fri, 21 Sep 2018 07:03:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C89252DB5D; Fri, 21 Sep 2018 07:03:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5BAB128F87 for ; Fri, 21 Sep 2018 07:03:22 +0000 (UTC) Received: from localhost ([::1]:54159 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3FTF-0004G9-7t for patchwork-qemu-devel@patchwork.kernel.org; Fri, 21 Sep 2018 03:03:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g3FRo-0002PM-Rr for qemu-devel@nongnu.org; Fri, 21 Sep 2018 03:01:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g3FRn-0005ap-TN for qemu-devel@nongnu.org; Fri, 21 Sep 2018 03:01:52 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53152) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g3FRl-0005Wb-JW; Fri, 21 Sep 2018 03:01:49 -0400 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.25]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E828A3082126; Fri, 21 Sep 2018 07:01:48 +0000 (UTC) Received: from laptop.redhat.com (ovpn-117-87.ams2.redhat.com [10.36.117.87]) by smtp.corp.redhat.com (Postfix) with ESMTP id A5C3D2015AD1; Fri, 21 Sep 2018 07:01:47 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Date: Fri, 21 Sep 2018 09:01:38 +0200 Message-Id: <20180921070138.10114-3-eric.auger@redhat.com> In-Reply-To: <20180921070138.10114-1-eric.auger@redhat.com> References: <20180921070138.10114-1-eric.auger@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.25 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.42]); Fri, 21 Sep 2018 07:01:49 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 2/2] hw/arm/smmuv3: fix eventq recording and IRQ triggerring X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The event queue management is broken today. Event records are not properly written as EVT_SET_* macro was not updating the actual event record. Also the event queue interrupt is not correctly triggered. Fixes: bb981004eaf4 ("hw/arm/smmuv3: Event queue recording helper") Signed-off-by: Eric Auger --- hw/arm/smmuv3-internal.h | 26 +++++++++++++------------- hw/arm/smmuv3.c | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index bab25d640e..19540f8f41 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -442,17 +442,17 @@ typedef struct SMMUEventInfo { #define EVT_Q_OVERFLOW (1 << 31) -#define EVT_SET_TYPE(x, v) deposit32((x)->word[0], 0 , 8 , v) -#define EVT_SET_SSV(x, v) deposit32((x)->word[0], 11, 1 , v) -#define EVT_SET_SSID(x, v) deposit32((x)->word[0], 12, 20, v) -#define EVT_SET_SID(x, v) ((x)->word[1] = v) -#define EVT_SET_STAG(x, v) deposit32((x)->word[2], 0 , 16, v) -#define EVT_SET_STALL(x, v) deposit32((x)->word[2], 31, 1 , v) -#define EVT_SET_PNU(x, v) deposit32((x)->word[3], 1 , 1 , v) -#define EVT_SET_IND(x, v) deposit32((x)->word[3], 2 , 1 , v) -#define EVT_SET_RNW(x, v) deposit32((x)->word[3], 3 , 1 , v) -#define EVT_SET_S2(x, v) deposit32((x)->word[3], 7 , 1 , v) -#define EVT_SET_CLASS(x, v) deposit32((x)->word[3], 8 , 2 , v) +#define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v)) +#define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v)) +#define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v)) +#define EVT_SET_SID(x, v) ((x)->word[1] = v) +#define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v)) +#define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v)) +#define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v)) +#define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v)) +#define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v)) +#define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v)) +#define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v)) #define EVT_SET_ADDR(x, addr) \ do { \ (x)->word[5] = (uint32_t)(addr >> 32); \ @@ -460,8 +460,8 @@ typedef struct SMMUEventInfo { } while (0) #define EVT_SET_ADDR2(x, addr) \ do { \ - deposit32((x)->word[7], 3, 29, addr >> 16); \ - deposit32((x)->word[7], 0, 16, addr & 0xffff);\ + (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \ + (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\ } while (0) void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bb6a24e9b8..8c4e99fecc 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -136,7 +136,7 @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt) return r; } - if (smmuv3_q_empty(q)) { + if (!smmuv3_q_empty(q)) { smmuv3_trigger_irq(s, SMMU_IRQ_EVTQ, 0); } return MEMTX_OK;