From patchwork Wed Oct 10 20:37:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lindsay X-Patchwork-Id: 10635239 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A3A116B1 for ; Wed, 10 Oct 2018 20:43:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25EA5252D5 for ; Wed, 10 Oct 2018 20:43:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 196F828979; Wed, 10 Oct 2018 20:43:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8642B252D5 for ; Wed, 10 Oct 2018 20:43:30 +0000 (UTC) Received: from localhost ([::1]:59059 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gALKL-0006st-RW for patchwork-qemu-devel@patchwork.kernel.org; Wed, 10 Oct 2018 16:43:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39809) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gALFi-0002wL-Gl for qemu-devel@nongnu.org; Wed, 10 Oct 2018 16:38:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gALFh-0002ju-CK for qemu-devel@nongnu.org; Wed, 10 Oct 2018 16:38:42 -0400 Received: from mail-yw1-xc44.google.com ([2607:f8b0:4864:20::c44]:43621) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gALFa-0002Uj-Oe; Wed, 10 Oct 2018 16:38:34 -0400 Received: by mail-yw1-xc44.google.com with SMTP id j75-v6so2716112ywj.10; Wed, 10 Oct 2018 13:38:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XSKOUQl9vmYg3HcpyWFwjAi/QFJzce6gGYliyVcFznE=; b=g16reVReXoKePBaxx+eU7KRtyu7j7tIvNe9sZVAWJD65TWxmtiVkmekQlZfEBlQgv+ NERx8GQ0o3ka3OOKzPoOPVaOT7yEbnBVMMc/UTZkopOgUodely24jsr8YHgbhEcVoC6m CQJdsEeICVHP+Lz8nhdsQfse8cfM/corRdfSDCktaITtP9zQaXM8X262NrEbkLn335Ch UwQAk7gx3/1b8xzgGp8kCNqzjvfg0KuP44d6LtzXroG0gEXfZBzqJHeHb69GG9xdJ3u8 kO0ida5gyuCiaee1UlCIvTweUoDqEMfBUtBGWmS01Dnml1hteCW3ydKwpDCfIobCuf69 VGyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XSKOUQl9vmYg3HcpyWFwjAi/QFJzce6gGYliyVcFznE=; b=fwnyyBXBl1W/iyF/Ofm3F/D48+a0iMsSEiZlv0f/OQAWg8IkmOdcHo3Svk+cftXOEq 8WDlSLsddE8pnioL4YgGHAe0eLIG2CKg0UBzzg9abwb/0YmVP7DBgHYb7qE0t0xG0tSv NPPK546A+j9ae0Nxsus9JupPeaKigkjBSgBJBHqWa2E1S3D37F4H0J0n4pTW9F2QBYWS AF0KPeeR6Ra34Z4L7sEPU6QxJJYa0d1aFiWG6NBgyxAFAO4crPP3h5WaZ4pkwNJiZ2/y cQLDlKWm5D2jXsCOxhfngdNwOEq8ngaPAQAuSdM2y6aWKmuCd5GUZiacUVYtIIv1cfaz I1jA== X-Gm-Message-State: ABuFfohbvsGrTS+lPFqJFiaRI/A/toD//c//r5D35kvTsJUx0pyXq6NF SbmzDSK9LbfNjJwapSYNviPaNhVB X-Google-Smtp-Source: ACcGV605J7NBmoB22gGeSW7fFpnPYdJwMFA+mxpfYKOHN0AzDOBab2M20Ale3SjNBpZCjvhxrGRmBw== X-Received: by 2002:a81:7a93:: with SMTP id v141-v6mr19516278ywc.100.1539203914004; Wed, 10 Oct 2018 13:38:34 -0700 (PDT) Received: from quinoa.localdomain ([216.85.170.153]) by smtp.gmail.com with ESMTPSA id u131-v6sm15170728ywf.13.2018.10.10.13.38.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Oct 2018 13:38:33 -0700 (PDT) From: Aaron Lindsay To: qemu-arm@nongnu.org, Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite Date: Wed, 10 Oct 2018 16:37:32 -0400 Message-Id: <20181010203735.27918-12-aclindsa@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181010203735.27918-1-aclindsa@gmail.com> References: <20181010203735.27918-1-aclindsa@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 Subject: [Qemu-devel] [PATCH v6 11/14] target/arm: PMU: Add instruction and cycle events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 90 ++++++++++++++++++++++----------------------- 1 file changed, 44 insertions(+), 46 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f0798f7a8c..d6501de1ba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -15,6 +15,7 @@ #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" +#include "sysemu/cpus.h" #include "sysemu/kvm.h" #include "fpu/softfloat.h" #include "qemu/range.h" @@ -988,9 +989,50 @@ typedef struct pm_event { uint64_t (*get_count)(CPUARMState *); } pm_event; +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +/* + * Return the underlying cycle count for the PMU cycle counters. If we're in + * usermode, simply return 0. + */ +static uint64_t cycles_get_count(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#else + return 0; +#endif +} + +#ifndef CONFIG_USER_ONLY +static bool instructions_supported(CPUARMState *env) +{ + return use_icount == 1 /* Precise instruction counting */; +} + +static uint64_t instructions_get_count(CPUARMState *env) +{ + return (uint64_t)cpu_get_icount_raw(); +} +#endif + static const pm_event pm_events[] = { +#ifndef CONFIG_USER_ONLY + { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ + .supported = instructions_supported, + .get_count = instructions_get_count, + }, + { .number = 0x011, /* CPU_CYCLES, Cycle */ + .supported = event_always_supported, + .get_count = cycles_get_count, + } +#endif }; -#define MAX_EVENT_ID 0x0 +#define MAX_EVENT_ID 0x11 #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; @@ -1083,8 +1125,6 @@ static CPAccessResult pmreg_access_swinc(CPUARMState *env, return pmreg_access(env, ri, isread); } -#ifndef CONFIG_USER_ONLY - static CPAccessResult pmreg_access_selr(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -1195,9 +1235,7 @@ static inline bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) */ void pmccntr_op_start(CPUARMState *env) { - uint64_t cycles = 0; - cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + uint64_t cycles = cycles_get_count(env); if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles = cycles; @@ -1343,42 +1381,6 @@ static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); } -#else /* CONFIG_USER_ONLY */ - -void pmccntr_op_start(CPUARMState *env) -{ -} - -void pmccntr_op_finish(CPUARMState *env) -{ -} - -void pmevcntr_op_start(CPUARMState *env, uint8_t i) -{ -} - -void pmevcntr_op_finish(CPUARMState *env, uint8_t i) -{ -} - -void pmu_op_start(CPUARMState *env) -{ -} - -void pmu_op_finish(CPUARMState *env) -{ -} - -void pmu_pre_el_change(ARMCPU *cpu, void *ignored) -{ -} - -void pmu_post_el_change(ARMCPU *cpu, void *ignored) -{ -} - -#endif - static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1752,7 +1754,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { /* Unimplemented so WI. */ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, -#ifndef CONFIG_USER_ONLY { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), @@ -1774,7 +1775,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), .readfn = pmccntr_read, .writefn = pmccntr_write, .raw_readfn = raw_read, .raw_writefn = raw_write, }, -#endif { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, .access = PL0_RW, .accessfn = pmreg_access, @@ -5416,7 +5416,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) * count register. */ unsigned int i, pmcrn = 4; -#ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr = { .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, .access = PL0_RW, @@ -5473,7 +5472,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } -#endif ARMCPRegInfo clidr = { .name = "CLIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,