diff mbox series

[v6,02/14] target/arm: Mask PMOVSR writes based on supported counters

Message ID 20181010203735.27918-3-aclindsa@gmail.com (mailing list archive)
State New, archived
Headers show
Series More fully implement ARM PMUv3 | expand

Commit Message

Aaron Lindsay Oct. 10, 2018, 8:37 p.m. UTC 
This is an amendment to my earlier patch:
    commit 7ece99b17e832065236c07a158dfac62619ef99b
    Author: Aaron Lindsay <alindsay@codeaurora.org>
    Date:   Thu Apr 26 11:04:39 2018 +0100

	target/arm: Mask PMU register writes based on PMCR_EL0.N

Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
---
 target/arm/helper.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Richard Henderson Oct. 15, 2018, 7:27 p.m. UTC | #1 
On 10/10/18 1:37 PM, Aaron Lindsay wrote:
> This is an amendment to my earlier patch:
>     commit 7ece99b17e832065236c07a158dfac62619ef99b
>     Author: Aaron Lindsay <alindsay@codeaurora.org>
>     Date:   Thu Apr 26 11:04:39 2018 +0100
> 
> 	target/arm: Mask PMU register writes based on PMCR_EL0.N
> 
> Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
> ---
>  target/arm/helper.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 52c76b7444..8ca4d30797 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1179,6 +1179,7 @@  static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
 {
+    value &= pmu_counter_mask(env);
     env->cp15.c9_pmovsr &= ~value;
 }