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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id g81-v6sm3869599ljf.34.2018.10.10.19.19.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Oct 2018 19:19:38 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 11 Oct 2018 04:19:23 +0200 Message-Id: <20181011021931.4249-5-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011021931.4249-1-edgar.iglesias@gmail.com> References: <20181011021931.4249-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::242 Subject: [Qemu-devel] [PATCH v2 04/12] net: cadence_gem: Add macro with max number of descriptor words X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com, philmd@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: "Edgar E. Iglesias" Add macro with max number of DMA descriptor words. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Edgar E. Iglesias --- hw/net/cadence_gem.c | 4 ++-- include/hw/net/cadence_gem.h | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 31f3fe0e81..4d769b0244 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, */ static void gem_transmit(CadenceGEMState *s) { - uint32_t desc[2]; + uint32_t desc[DESC_MAX_NUM_WORDS]; hwaddr packet_desc_addr; uint8_t tx_packet[2048]; uint8_t *p; @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { - uint32_t desc_first[2]; + uint32_t desc_first[DESC_MAX_NUM_WORDS]; /* Modify the 1st descriptor of this packet to be owned by * the processor. diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 633d564dc3..b33ef6513b 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -32,6 +32,9 @@ #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ +/* Max number of words in a DMA descriptor. */ +#define DESC_MAX_NUM_WORDS 2 + #define MAX_PRIORITY_QUEUES 8 #define MAX_TYPE1_SCREENERS 16 #define MAX_TYPE2_SCREENERS 16 @@ -74,7 +77,7 @@ typedef struct CadenceGEMState { uint8_t can_rx_state; /* Debug only */ - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; bool sar_active[4]; } CadenceGEMState;