From patchwork Fri Oct 12 17:30:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10639027 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4793213AD for ; Fri, 12 Oct 2018 17:44:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3773827FC0 for ; Fri, 12 Oct 2018 17:44:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2B36B2B753; Fri, 12 Oct 2018 17:44:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9DC332BB49 for ; Fri, 12 Oct 2018 17:44:04 +0000 (UTC) Received: from localhost ([::1]:41950 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Tn-0003V8-SZ for patchwork-qemu-devel@patchwork.kernel.org; Fri, 12 Oct 2018 13:44:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39855) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Hh-0001qr-PL for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1Hd-0000F8-LP for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:33 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:60398) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1Hb-0008U6-RX for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:28 -0400 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 zuban) id 1gB1HO-0003CQ-Kb; Fri, 12 Oct 2018 19:31:14 +0200 Received: from mail.uni-paderborn.de by pova with queue id 2932988-2; Fri, 12 Oct 2018 17:31:14 GMT X-Envelope-From: Received: from aftr-95-222-26-80.unity-media.net ([95.222.26.80] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 nylar) id 1gB1HO-0006OT-N9; Fri, 12 Oct 2018 19:31:14 +0200 From: Bastian Koppelmann To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:31 +0200 Message-Id: <20181012173047.25420-13-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 28 +++ target/riscv/insn_trans/trans_rvd.inc.c | 313 ++++++++++++++++++++++++ target/riscv/translate.c | 1 + 3 files changed, 342 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a629a717dc..1e4ef4f8cc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -202,3 +202,31 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm + +# *** RV32D Standard Extension *** +fld ............ ..... 011 ..... 0000111 @i +fsd ....... ..... ..... 011 ..... 0100111 @s +fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm +fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm +fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm +fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm +fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm +fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm +fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm +fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm +fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm +fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r +fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r +fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r +fmin_d 0010101 ..... ..... 000 ..... 1010011 @r +fmax_d 0010101 ..... ..... 001 ..... 1010011 @r +fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm +fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm +feq_d 1010001 ..... ..... 010 ..... 1010011 @r +flt_d 1010001 ..... ..... 001 ..... 1010011 @r +fle_d 1010001 ..... ..... 000 ..... 1010011 @r +fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 +fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm +fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm +fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm +fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c new file mode 100644 index 0000000000..7120afa9be --- /dev/null +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -0,0 +1,313 @@ +/* + * RISC-V translation routines for the RV64D Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool trans_fld(DisasContext *ctx, arg_fld *a, uint32_t insn) +{ + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fsd(DisasContext *ctx, arg_fsd *a, uint32_t insn) +{ + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a, uint32_t insn) +{ + gen_set_rm(ctx, a->rm); + gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a, uint32_t insn) +{ + gen_set_rm(ctx, a->rm); + gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a, uint32_t insn) +{ + gen_set_rm(ctx, a->rm); + gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a, uint32_t insn) +{ + gen_set_rm(ctx, a->rm); + gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + return true; +} + +static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a, uint32_t insn) +{ + if (a->rs1 == a->rs2) { /* FMOV */ + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + } else { + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], + cpu_fpr[a->rs1], 0, 63); + } + return true; +} + +static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a, uint32_t insn) +{ + if (a->rs1 == a->rs2) { /* FNEG */ + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63); + tcg_temp_free_i64(t0); + } + return true; +} + +static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a, uint32_t insn) +{ + if (a->rs1 == a->rs2) { /* FABS */ + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(); + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN); + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); + tcg_temp_free_i64(t0); + } + return true; +} + +static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + return true; +} + +static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a, uint32_t insn) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + return true; +} + +static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn) +{ +#if defined(TARGET_RISCV64) + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); +#else + gen_exception_illegal(ctx); +#endif + return true; +} + +static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a, uint32_t insn) +{ + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a, uint32_t insn) +{ + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a, uint32_t insn) +{ + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 558cc4cfc0..e19398ce10 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1504,6 +1504,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rvm.inc.c" #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" +#include "insn_trans/trans_rvd.inc.c" static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) {