From patchwork Fri Oct 12 17:30:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10639011 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A9F51112B for ; Fri, 12 Oct 2018 17:38:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61CC62AA5D for ; Fri, 12 Oct 2018 17:38:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 53CB02B474; Fri, 12 Oct 2018 17:38:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 307FB2AA5D for ; Fri, 12 Oct 2018 17:38:13 +0000 (UTC) Received: from localhost ([::1]:41920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1O9-00077f-3W for patchwork-qemu-devel@patchwork.kernel.org; Fri, 12 Oct 2018 13:38:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39677) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1HO-0001cw-WC for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1HK-0008Ph-Qd for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:14 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:55232) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1HK-0008Od-EF for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:10 -0400 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 nylar) id 1gB1HI-0006QY-OV; Fri, 12 Oct 2018 19:31:08 +0200 Received: from mail.uni-paderborn.de by wormulon with queue id 2934317-5; Fri, 12 Oct 2018 17:31:08 GMT X-Envelope-From: Received: from aftr-95-222-26-80.unity-media.net ([95.222.26.80] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 nylar) id 1gB1HI-0006OT-NQ; Fri, 12 Oct 2018 19:31:08 +0200 From: Bastian Koppelmann To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:21 +0200 Message-Id: <20181012173047.25420-3-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 02/28] target/riscv: Convert RVXI branch insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 19 +++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 52 +++++++++++++++++++++++++ target/riscv/translate.c | 19 +-------- 3 files changed, 72 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 44d4e922b6..b49913416d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -17,14 +17,33 @@ # this program. If not, see . # Fields: +%rs2 20:5 +%rs1 15:5 %rd 7:5 # immediates: +%imm_i 20:s12 +%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 +%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 %imm_u 12:s20 !function=ex_shift_12 +# Argument sets: +&branch imm rs2 rs1 + # Formats 32: +@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd +@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd +@j .................... ..... ....... imm=%imm_j %rd # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u +jal .................... ..... 1101111 @j +jalr ............ ..... 000 ..... 1100111 @i +beq ....... ..... ..... 000 ..... 1100011 @b +bne ....... ..... ..... 001 ..... 1100011 @b +blt ....... ..... ..... 100 ..... 1100011 @b +bge ....... ..... ..... 101 ..... 1100011 @b +bltu ....... ..... ..... 110 ..... 1100011 @b +bgeu ....... ..... ..... 111 ..... 1100011 @b diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index aee0d1637d..83345d71d7 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -33,3 +33,55 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn) } return true; } + +static bool trans_jal(DisasContext *ctx, arg_jal *a, uint32_t insn) +{ + CPURISCVState *env = current_cpu->env_ptr; + gen_jal(env, ctx, a->rd, a->imm); + return true; +} + +static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn) +{ + CPURISCVState *env = current_cpu->env_ptr; + gen_jalr(env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn) +{ + CPURISCVState *env = current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bne(DisasContext *ctx, arg_bne *a, uint32_t insn) +{ + CPURISCVState *env = current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_blt(DisasContext *ctx, arg_blt *a, uint32_t insn) +{ + CPURISCVState *env = current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bge(DisasContext *ctx, arg_bge *a, uint32_t insn) +{ + CPURISCVState *env = current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bltu(DisasContext *ctx, arg_bltu *a, uint32_t insn) +{ + CPURISCVState *env = current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn) +{ + + CPURISCVState *env = current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2ee886c6b7..8181ad7419 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1671,6 +1671,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) { \ return imm << amount; \ } +EX_SH(1) EX_SH(12) bool decode_insn32(DisasContext *ctx, uint32_t insn); @@ -1699,24 +1700,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_AUIPC: - if (rd == 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) + - ctx->base.pc_next); - break; - case OPC_RISC_JAL: - imm = GET_JAL_IMM(ctx->opcode); - gen_jal(env, ctx, rd, imm); - break; - case OPC_RISC_JALR: - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_BRANCH: - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, - GET_B_IMM(ctx->opcode)); - break; case OPC_RISC_LOAD: gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); break;