From patchwork Fri Oct 12 17:30:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10639019 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 748E6112B for ; Fri, 12 Oct 2018 17:41:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64C412C2B1 for ; Fri, 12 Oct 2018 17:41:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 631B92C2F6; Fri, 12 Oct 2018 17:41:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BABC22C2B1 for ; Fri, 12 Oct 2018 17:41:16 +0000 (UTC) Received: from localhost ([::1]:41937 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1R6-00014B-1I for patchwork-qemu-devel@patchwork.kernel.org; Fri, 12 Oct 2018 13:41:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39686) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1HP-0001d2-0f for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1HM-0008Rs-VG for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:14 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:33814) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1HM-0008R9-Jx for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:12 -0400 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 hoth) id 1gB1HL-00065C-Rj; Fri, 12 Oct 2018 19:31:11 +0200 Received: from mail.uni-paderborn.de by tweenies with queue id 2903156-4; Fri, 12 Oct 2018 17:31:11 GMT X-Envelope-From: Received: from aftr-95-222-26-80.unity-media.net ([95.222.26.80] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 nylar) id 1gB1HL-0006OT-NZ; Fri, 12 Oct 2018 19:31:11 +0200 From: Bastian Koppelmann To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:26 +0200 Message-Id: <20181012173047.25420-8-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 17 +++++ target/riscv/insn_trans/trans_rvm.inc.c | 87 +++++++++++++++++++++++++ target/riscv/translate.c | 10 +-- 3 files changed, 105 insertions(+), 9 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index dbb177395d..15dd6234a4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -114,3 +114,20 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r sllw 0000000 ..... ..... 001 ..... 0111011 @r srlw 0000000 ..... ..... 101 ..... 0111011 @r sraw 0100000 ..... ..... 101 ..... 0111011 @r + +# *** RV32M Standard Extension *** +mul 0000001 ..... ..... 000 ..... 0110011 @r +mulh 0000001 ..... ..... 001 ..... 0110011 @r +mulhsu 0000001 ..... ..... 010 ..... 0110011 @r +mulhu 0000001 ..... ..... 011 ..... 0110011 @r +div 0000001 ..... ..... 100 ..... 0110011 @r +divu 0000001 ..... ..... 101 ..... 0110011 @r +rem 0000001 ..... ..... 110 ..... 0110011 @r +remu 0000001 ..... ..... 111 ..... 0110011 @r + +# *** RV64M Standard Extension (in addition to RV32M) *** +mulw 0000001 ..... ..... 000 ..... 0111011 @r +divw 0000001 ..... ..... 100 ..... 0111011 @r +divuw 0000001 ..... ..... 101 ..... 0111011 @r +remw 0000001 ..... ..... 110 ..... 0111011 @r +remuw 0000001 ..... ..... 111 ..... 0111011 @r diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.inc.c new file mode 100644 index 0000000000..2d0fd6a64f --- /dev/null +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -0,0 +1,87 @@ +/* + * RISC-V translation routines for the RV64M Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + + +static bool trans_mul(DisasContext *ctx, arg_mul *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_mulh(DisasContext *ctx, arg_mulh *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_div(DisasContext *ctx, arg_div *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_divu(DisasContext *ctx, arg_divu *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_rem(DisasContext *ctx, arg_rem *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_remu(DisasContext *ctx, arg_remu *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2); + return true; +} +static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7438205492..7c1ecfaf1b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1638,6 +1638,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "decode_insn32.inc.c" /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" +#include "insn_trans/trans_rvm.inc.c" static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { @@ -1659,15 +1660,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_ARITH: -#if defined(TARGET_RISCV64) - case OPC_RISC_ARITH_W: -#endif - if (rd == 0) { - break; /* NOP */ - } - gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2); - break; case OPC_RISC_FP_LOAD: gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm); break;