From patchwork Wed Oct 17 21:54:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10646111 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C209F13B0 for ; Wed, 17 Oct 2018 22:05:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF8FA288FC for ; Wed, 17 Oct 2018 22:05:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9F83E289A2; Wed, 17 Oct 2018 22:05:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 07520288FC for ; Wed, 17 Oct 2018 22:05:27 +0000 (UTC) Received: from localhost ([::1]:39292 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCtwU-000802-Dt for patchwork-qemu-devel@patchwork.kernel.org; Wed, 17 Oct 2018 18:05:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCtto-0006QM-Fm for qemu-devel@nongnu.org; Wed, 17 Oct 2018 18:02:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCttm-0005j3-BL for qemu-devel@nongnu.org; Wed, 17 Oct 2018 18:02:40 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:45315) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCttk-0005VR-J4 for qemu-devel@nongnu.org; Wed, 17 Oct 2018 18:02:38 -0400 Received: by mail-pg1-x544.google.com with SMTP id t70-v6so13156470pgd.12 for ; Wed, 17 Oct 2018 15:02:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=uVgKKvLLbNTYlmvsyXQt3Q0SAOZzq1JpqM2F5a06AjQ=; b=BUMC/aIqwbABDr0/0kH0jrDNigoQAVtyiztYGQSESo07xrQcP3G4wQhweQoH6g1eNd oRXH4LBw36QW6eqa5czYTQB7SBpydEesdP4OVgZjvtOeyscaU3cQCEypTFjCJx8RjDSC LjPmVuUUQ/61JhD1AYwYFRON7no1dP2QQqI5EQt5ffz+9YBZYV5ScbFzr+zM6IfTwG5s UNlUs2nZmOxieYEY+oUMB1sW5+42qNya7NujYcNI9JpqTAP/mGQ0gDaLe4bqhW+8YH2I wgyp+Sgt7FFtM74W+Be6Dda5C+vPyhrK6YS09sjOYPg+D+79y6FpBgMxeAVVOdyzD3Dd dZhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=uVgKKvLLbNTYlmvsyXQt3Q0SAOZzq1JpqM2F5a06AjQ=; b=s6KoPCwNY+lypyWnlq1UvkT8cFIsDkOiWvXOjMljRG4EUf5f22Bad6k/a8/ucABkZb NIyfDjs7i6kbTZeakKOsnDemSvqq2cxPD6PtjLH5Ef2MSlC9HePUAU1nIL19D0TQTBO4 RnsOPjcU2gm76k9FGle0qUVNgQ4DjrTWtaKBlMvQWmMz4zyMW28Pfh/lk4MnYhUo87pX XOXSeVmM1pxyBalTQ5jSOvC6+3dTsePPF2SeEZpa/Mr4RftuKS1Jy2pDSyOjxLwH9zWV bji4N3rl5fPDZ9MhmpW/YY0gzur1yl4emDRT2s1RH9Y7bLR1CsmvM2EmnuZo6dXxO2BK 2CQg== X-Gm-Message-State: ABuFfogfARTFVjpKxyDiQNb+uMohctYOc3yLP+Anhjnky+LTEB7NqRVe nqPk9Q3k5476yHhJ0YP2uRHN+A== X-Google-Smtp-Source: ACcGV62U5F/9lavJ+02Jwvc4Y5kcRkNZ7VoA4AGQYm+NKwAutHSD5VBTFuYaAaQz5QfbP2gq9FPIbQ== X-Received: by 2002:a63:3747:: with SMTP id g7-v6mr26699873pgn.59.1539813744104; Wed, 17 Oct 2018 15:02:24 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id p24-v6sm24771670pgm.70.2018.10.17.15.02.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Oct 2018 15:02:23 -0700 (PDT) Date: Wed, 17 Oct 2018 14:54:19 -0700 Message-Id: <20181017215422.3973-3-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181017215422.3973-1-palmer@sifive.com> References: <20181017215422.3973-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PULL 2/5] RISC-V: Move non-ops from op_helper to cpu_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Clark , Alistair Francis , qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark This patch makes op_helper.c contain only instruction operation helpers used by translate.c and moves any unrelated cpu helpers into cpu_helper.c. No logic is changed by this patch. Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Palmer Dabbelt Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 2 +- target/riscv/{helper.c => cpu_helper.c} | 35 ++++++++++++++++++++++++- target/riscv/op_helper.c | 34 ------------------------ 3 files changed, 35 insertions(+), 36 deletions(-) rename target/riscv/{helper.c => cpu_helper.c} (95%) diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index abd0a7cde333..fcc5d34c1f2e 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1 +1 @@ -obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o pmp.o +obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o gdbstub.o pmp.o diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c similarity index 95% rename from target/riscv/helper.c rename to target/riscv/cpu_helper.c index 63b3386b765e..86f9f4730c88 100644 --- a/target/riscv/helper.c +++ b/target/riscv/cpu_helper.c @@ -1,5 +1,5 @@ /* - * RISC-V emulation helpers for qemu. + * RISC-V CPU helpers for qemu. * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu * Copyright (c) 2017-2018 SiFive, Inc. @@ -72,6 +72,39 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #if !defined(CONFIG_USER_ONLY) +/* iothread_mutex must be held */ +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) +{ + CPURISCVState *env = &cpu->env; + uint32_t old, new, cmp = atomic_read(&env->mip); + + do { + old = cmp; + new = (old & ~mask) | (value & mask); + cmp = atomic_cmpxchg(&env->mip, old, new); + } while (old != cmp); + + if (new && !old) { + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + } else if (!new && old) { + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + } + + return old; +} + +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv) +{ + if (newpriv > PRV_M) { + g_assert_not_reached(); + } + if (newpriv == PRV_H) { + newpriv = PRV_U; + } + /* tlb_flush is unnecessary as mode is contained in mmu_idx */ + env->priv = newpriv; +} + /* get_physical_address - get the physical address for this virtual address * * Do a page table walk to obtain the physical address corresponding to a diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index d0883d329b41..495390ab1c32 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -654,39 +654,6 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, #ifndef CONFIG_USER_ONLY -/* iothread_mutex must be held */ -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) -{ - CPURISCVState *env = &cpu->env; - uint32_t old, new, cmp = atomic_read(&env->mip); - - do { - old = cmp; - new = (old & ~mask) | (value & mask); - cmp = atomic_cmpxchg(&env->mip, old, new); - } while (old != cmp); - - if (new && !old) { - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); - } else if (!new && old) { - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); - } - - return old; -} - -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv) -{ - if (newpriv > PRV_M) { - g_assert_not_reached(); - } - if (newpriv == PRV_H) { - newpriv = PRV_U; - } - /* tlb_flush is unnecessary as mode is contained in mmu_idx */ - env->priv = newpriv; -} - target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) { if (!(env->priv >= PRV_S)) { @@ -737,7 +704,6 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) return retpc; } - void helper_wfi(CPURISCVState *env) { CPUState *cs = CPU(riscv_env_get_cpu(env));