From patchwork Thu Oct 25 14:45:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emilio Cota X-Patchwork-Id: 10656107 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F7D213A9 for ; Thu, 25 Oct 2018 15:47:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DD792BDD6 for ; Thu, 25 Oct 2018 15:47:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 822762BDDD; Thu, 25 Oct 2018 15:47:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 454682BDD6 for ; Thu, 25 Oct 2018 15:47:00 +0000 (UTC) Received: from localhost ([::1]:55275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFhqd-0001sE-H3 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 25 Oct 2018 11:46:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gFh5O-00034O-3B for qemu-devel@nongnu.org; Thu, 25 Oct 2018 10:58:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gFgvD-0008Aj-22 for qemu-devel@nongnu.org; Thu, 25 Oct 2018 10:47:42 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:37367) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gFgvB-0007mc-MI; Thu, 25 Oct 2018 10:47:38 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id B5C0420CE1; Thu, 25 Oct 2018 10:46:49 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Thu, 25 Oct 2018 10:46:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=UPgyFhU0ld2aOH0gfsuxY1SsvFtG9HAn2Q6MqTjF/88=; b=Pj51D JszcUqvzfwyj5yiRbrp4kjchXlTc9jYgEs/LnFRtNVFzrO36Tr4gxAQqkbmvdp6D /0KXotadmdY/01QdN5gmqP1yDE+I+M1SdqWTPmgcYV0gxGaTa7hX3KOdGKEbgLxe hOq90OczXZ3qZbq5UJxrQgYS1d/vXZh/WZ/3Ps= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=UPgyFhU0ld2aOH0gfsuxY1SsvFtG9 HAn2Q6MqTjF/88=; b=pex03MgWv0KlfbmSLyHud1yovHEBeVX2XkTG/A8LAI53s TkU1IgENLQ3SuVG4dilF/EdhZZmR3lT4v3iLr4530gS+S8sUcGK+0K5e7bgZUwPX xZkYWQqDGgsEpVssf9v0+NCA4786Gm2+MVyhiPAmqEilg9EC40rEa2QLCBUDzuEs YDk4WWY/jifv34GfOmOPqLeiWXApUfGIr7/k45UoB40gffKT91GIrEfpARvwfzmm Y3xRmWFUCgNhizngRRZUeYzb1zXEeTTWKF4Bda+aga1m3fJoOsgHrXnTmuHkWxhD wF+1zRgKAFpEplhS4vzvmBgAJJRilhIlMy2/DwD5Q== X-ME-Sender: X-ME-Proxy: Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 40294E47C6; Thu, 25 Oct 2018 10:46:49 -0400 (EDT) From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Thu, 25 Oct 2018 10:45:50 -0400 Message-Id: <20181025144644.15464-17-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181025144644.15464-1-cota@braap.org> References: <20181025144644.15464-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC v4 17/71] ppc: convert to cpu_halted X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Paolo Bonzini , Richard Henderson , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP In ppce500_spin.c, acquire the lock just once to update both cpu->halted and cpu->stopped. In hw/ppc/spapr_hcall.c, acquire the lock just once to update cpu->halted and call cpu_has_work, since later in the series we'll acquire the BQL (if not already held) from cpu_has_work. Cc: David Gibson Cc: Alexander Graf Cc: qemu-ppc@nongnu.org Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/ppc/helper_regs.h | 2 +- hw/ppc/e500.c | 4 ++-- hw/ppc/ppc.c | 10 +++++----- hw/ppc/ppce500_spin.c | 6 ++++-- hw/ppc/spapr_cpu_core.c | 4 ++-- hw/ppc/spapr_hcall.c | 4 +++- hw/ppc/spapr_rtas.c | 6 +++--- target/ppc/excp_helper.c | 4 ++-- target/ppc/kvm.c | 4 ++-- target/ppc/translate_init.inc.c | 6 +++--- 10 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 5efd18049e..9298052ac5 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -161,7 +161,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, #if !defined(CONFIG_USER_ONLY) if (unlikely(msr_pow == 1)) { if (!env->pending_interrupts && (*env->check_pow)(env)) { - cs->halted = 1; + cpu_halted_set(cs, 1); excp = EXCP_HALTED; } } diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e6747fce28..6843c545b7 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -657,7 +657,7 @@ static void ppce500_cpu_reset_sec(void *opaque) /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ - cs->halted = 1; + cpu_halted_set(cs, 1); cs->exception_index = EXCP_HLT; } @@ -671,7 +671,7 @@ static void ppce500_cpu_reset(void *opaque) cpu_reset(cs); /* Set initial guest state. */ - cs->halted = 0; + cpu_halted_set(cs, 0); env->gpr[1] = (16 * MiB) - 8; env->gpr[3] = bi->dt_base; env->gpr[4] = 0; diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index ec4be25f49..d1a5a0b877 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -151,7 +151,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int level) /* XXX: Note that the only way to restart the CPU is to reset it */ if (level) { LOG_IRQ("%s: stop the CPU\n", __func__); - cs->halted = 1; + cpu_halted_set(cs, 1); } break; case PPC6xx_INPUT_HRESET: @@ -230,10 +230,10 @@ static void ppc970_set_irq(void *opaque, int pin, int level) /* XXX: TODO: relay the signal to CKSTP_OUT pin */ if (level) { LOG_IRQ("%s: stop the CPU\n", __func__); - cs->halted = 1; + cpu_halted_set(cs, 1); } else { LOG_IRQ("%s: restart the CPU\n", __func__); - cs->halted = 0; + cpu_halted_set(cs, 0); qemu_cpu_kick(cs); } break; @@ -361,10 +361,10 @@ static void ppc40x_set_irq(void *opaque, int pin, int level) /* Level sensitive - active low */ if (level) { LOG_IRQ("%s: stop the CPU\n", __func__); - cs->halted = 1; + cpu_halted_set(cs, 1); } else { LOG_IRQ("%s: restart the CPU\n", __func__); - cs->halted = 0; + cpu_halted_set(cs, 0); qemu_cpu_kick(cs); } break; diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index c45fc858de..4b3532730f 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -107,9 +107,11 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data) map_start = ldq_p(&curspin->addr) & ~(map_size - 1); mmubooke_create_initial_mapping(env, 0, map_start, map_size); - cs->halted = 0; - cs->exception_index = -1; + cpu_mutex_lock(cs); + cpu_halted_set(cs, 0); cs->stopped = false; + cpu_mutex_unlock(cs); + cs->exception_index = -1; qemu_cpu_kick(cs); } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 2398ce62c0..4c9c60b53b 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -37,7 +37,7 @@ static void spapr_cpu_reset(void *opaque) /* All CPUs start halted. CPU0 is unhalted from the machine level * reset code and the rest are explicitly started up by the guest * using an RTAS call */ - cs->halted = 1; + cpu_halted_set(cs, 1); /* Set compatibility mode to match the boot CPU, which was either set * by the machine reset code or by CAS. This should never fail. @@ -91,7 +91,7 @@ void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r env->nip = nip; env->gpr[3] = r3; kvmppc_set_reg_ppc_online(cpu, 1); - CPU(cpu)->halted = 0; + cpu_halted_set(CPU(cpu), 0); /* Enable Power-saving mode Exit Cause exceptions */ ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index ae913d070f..9891fc7740 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1088,11 +1088,13 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, env->msr |= (1ULL << MSR_EE); hreg_compute_hflags(env); + cpu_mutex_lock(cs); if (!cpu_has_work(cs)) { - cs->halted = 1; + cpu_halted_set(cs, 1); cs->exception_index = EXCP_HLT; cs->exit_request = 1; } + cpu_mutex_unlock(cs); return H_SUCCESS; } diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index d6a0952154..925f67123c 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -109,7 +109,7 @@ static void rtas_query_cpu_stopped_state(PowerPCCPU *cpu_, id = rtas_ld(args, 0); cpu = spapr_find_cpu(id); if (cpu != NULL) { - if (CPU(cpu)->halted) { + if (cpu_halted(CPU(cpu))) { rtas_st(rets, 1, 0); } else { rtas_st(rets, 1, 2); @@ -153,7 +153,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, sPAPRMachineState *spapr, env = &newcpu->env; pcc = POWERPC_CPU_GET_CLASS(newcpu); - if (!CPU(newcpu)->halted) { + if (!cpu_halted(CPU(newcpu))) { rtas_st(rets, 0, RTAS_OUT_HW_ERROR); return; } @@ -207,7 +207,7 @@ static void rtas_stop_self(PowerPCCPU *cpu, sPAPRMachineState *spapr, * This could deliver an interrupt on a dying CPU and crash the * guest */ ppc_store_lpcr(cpu, env->spr[SPR_LPCR] & ~pcc->lpcr_pm); - cs->halted = 1; + cpu_halted_set(cs, 1); kvmppc_set_reg_ppc_online(cpu, 0); qemu_cpu_kick(cs); } diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0ec7ae1ad4..5e1778584a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -206,7 +206,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) qemu_log("Machine check while not allowed. " "Entering checkstop state\n"); } - cs->halted = 1; + cpu_halted_set(cs, 1); cpu_interrupt_exittb(cs); } if (env->msr_mask & MSR_HVB) { @@ -954,7 +954,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) CPUState *cs; cs = CPU(ppc_env_get_cpu(env)); - cs->halted = 1; + cpu_halted_set(cs, 1); env->in_pm_state = true; /* The architecture specifies that HDEC interrupts are diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 30aeafa7de..dc6b8d5e9e 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1368,7 +1368,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) int kvm_arch_process_async_events(CPUState *cs) { - return cs->halted; + return cpu_halted(cs); } static int kvmppc_handle_halt(PowerPCCPU *cpu) @@ -1377,7 +1377,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu) CPUPPCState *env = &cpu->env; if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { - cs->halted = 1; + cpu_halted_set(cs, 1); cs->exception_index = EXCP_HLT; } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 263e63cb03..0e423bea69 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8445,7 +8445,7 @@ static bool cpu_has_work_POWER7(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - if (cs->halted) { + if (cpu_halted(cs)) { if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { return false; } @@ -8599,7 +8599,7 @@ static bool cpu_has_work_POWER8(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - if (cs->halted) { + if (cpu_halted(cs)) { if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { return false; } @@ -8791,7 +8791,7 @@ static bool cpu_has_work_POWER9(CPUState *cs) PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; - if (cs->halted) { + if (cpu_halted(cs)) { if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { return false; }