diff mbox series

[RFC,v4,53/71] sparc: convert to cpu_interrupt_request

Message ID 20181025144644.15464-53-cota@braap.org (mailing list archive)
State New, archived
Headers show
Series [RFC,v4,01/71] cpu: convert queued work to a QSIMPLEQ | expand

Commit Message

Emilio Cota Oct. 25, 2018, 2:46 p.m. UTC
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
 hw/sparc64/sparc64.c | 4 ++--
 target/sparc/cpu.c   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

Alex Bennée Oct. 31, 2018, 4:40 p.m. UTC | #1
Emilio G. Cota <cota@braap.org> writes:

> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Cc: Artyom Tarasenko <atar4qemu@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Emilio G. Cota <cota@braap.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  hw/sparc64/sparc64.c | 4 ++--
>  target/sparc/cpu.c   | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
> index 372bbd4f5b..58faeb111a 100644
> --- a/hw/sparc64/sparc64.c
> +++ b/hw/sparc64/sparc64.c
> @@ -56,7 +56,7 @@ void cpu_check_irqs(CPUSPARCState *env)
>      /* The bit corresponding to psrpil is (1<< psrpil), the next bit
>         is (2 << psrpil). */
>      if (pil < (2 << env->psrpil)) {
> -        if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> +        if (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) {
>              trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
>              env->interrupt_index = 0;
>              cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> @@ -87,7 +87,7 @@ void cpu_check_irqs(CPUSPARCState *env)
>                  break;
>              }
>          }
> -    } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> +    } else if (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) {
>          trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
>                                                env->interrupt_index);
>          env->interrupt_index = 0;
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 0f090ece54..88427283c1 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -709,7 +709,7 @@ static bool sparc_cpu_has_work(CPUState *cs)
>      SPARCCPU *cpu = SPARC_CPU(cs);
>      CPUSPARCState *env = &cpu->env;
>
> -    return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
> +    return (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) &&
>             cpu_interrupts_enabled(env);
>  }


--
Alex Bennée
Alex Bennée Oct. 31, 2018, 4:42 p.m. UTC | #2
Emilio G. Cota <cota@braap.org> writes:

> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Cc: Artyom Tarasenko <atar4qemu@gmail.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Emilio G. Cota <cota@braap.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  hw/sparc64/sparc64.c | 4 ++--
>  target/sparc/cpu.c   | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
> index 372bbd4f5b..58faeb111a 100644
> --- a/hw/sparc64/sparc64.c
> +++ b/hw/sparc64/sparc64.c
> @@ -56,7 +56,7 @@ void cpu_check_irqs(CPUSPARCState *env)
>      /* The bit corresponding to psrpil is (1<< psrpil), the next bit
>         is (2 << psrpil). */
>      if (pil < (2 << env->psrpil)) {
> -        if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> +        if (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) {
>              trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
>              env->interrupt_index = 0;
>              cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
> @@ -87,7 +87,7 @@ void cpu_check_irqs(CPUSPARCState *env)
>                  break;
>              }
>          }
> -    } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
> +    } else if (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) {
>          trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
>                                                env->interrupt_index);
>          env->interrupt_index = 0;
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 0f090ece54..88427283c1 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -709,7 +709,7 @@ static bool sparc_cpu_has_work(CPUState *cs)
>      SPARCCPU *cpu = SPARC_CPU(cs);
>      CPUSPARCState *env = &cpu->env;
>
> -    return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
> +    return (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) &&
>             cpu_interrupts_enabled(env);
>  }


--
Alex Bennée
diff mbox series

Patch

diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c
index 372bbd4f5b..58faeb111a 100644
--- a/hw/sparc64/sparc64.c
+++ b/hw/sparc64/sparc64.c
@@ -56,7 +56,7 @@  void cpu_check_irqs(CPUSPARCState *env)
     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
        is (2 << psrpil). */
     if (pil < (2 << env->psrpil)) {
-        if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+        if (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) {
             trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
             env->interrupt_index = 0;
             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
@@ -87,7 +87,7 @@  void cpu_check_irqs(CPUSPARCState *env)
                 break;
             }
         }
-    } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
+    } else if (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) {
         trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
                                               env->interrupt_index);
         env->interrupt_index = 0;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 0f090ece54..88427283c1 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -709,7 +709,7 @@  static bool sparc_cpu_has_work(CPUState *cs)
     SPARCCPU *cpu = SPARC_CPU(cs);
     CPUSPARCState *env = &cpu->env;
 
-    return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+    return (cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) &&
            cpu_interrupts_enabled(env);
 }